I would like to feed two processors with the same MIPI CSI2 camera. I cannot afford to have one of the processors to play the role of proxy to the other.

Though I searched hard, I'm not aware of any chip that can really duplicate (not mux) a CSI2 -+ lane.

Therefore, I have tried to do something similar to what is explained in this paper: http://www.intersil.com/content/dam/Intersil/documents/an17/an1787.pdf

CSI2 duplication

But it's not working.

Is there any way I could manage to duplicate a CSI2 signal?

Edit 1

Not working means that the signal is altered and the receiver(s) can't manage to decode data. Unfortunately, I don't have a good scope so I can't show an eye diagram.

LVDS is close to CSI2 so I tried that option.

There is definitely a problem of "amount of termination", which is supposed to be "fixed" by the resistors. I have tried different values / configurations, but it's the same problem. I have also tried different muxing / configurations in the receivers.

  • \$\begingroup\$ You're going to have to be more specific than 'it's not working'. Note that these are high speed serial buses so you need to use controlled impedance layout techniques. Also, the document you linked is for LVDS links. I don't know if the same techniques would work for MIPI as I don't know anything about the MIPI electrical spec. \$\endgroup\$ – alex.forencich Sep 21 '15 at 18:09
  • \$\begingroup\$ Did you simulate before trying this? Also a CPLD could have received the MIPI data and then sent it out as two separate channels. I really wouldn't expect a configuration like this to work for MIPI... \$\endgroup\$ – Some Hardware Guy Sep 21 '15 at 19:07
  • \$\begingroup\$ Please pay attention to the paper's remarks about the need to maintain a constant 50-ohm impedance through the splitter. Did you design a 4-layer PC board? Did you use proper twisted pair cables all the way through? \$\endgroup\$ – WhatRoughBeast Sep 22 '15 at 1:46
  • \$\begingroup\$ @SomeHardwareGuy Really, a CPLD? I think you would need to throw a full FPGA at this, unless there are CPLDs with serdes modules available. Of course I could be mistaken about the serial rates used in MIPI CSI2. \$\endgroup\$ – alex.forencich Sep 22 '15 at 8:39
  • \$\begingroup\$ Also, I presume you built this on a custom board? Can you show a picture of your exact setup? \$\endgroup\$ – alex.forencich Sep 22 '15 at 8:40

I have managed to do this CSI2 signal "duplication" by developing a MachXO3L FPGA. I have provided further information here.


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