Many applications use PLL's to generate frequencies where long-term frequency accuracy is necessary, but where a certain amount of short-term jitter might be acceptable. I've seen a number of devices with very-low-current low-to-moderate-precision oscillators, and was wondering whether it would be practical for device manufacturers to reduce device current consumption by replacing PLL's with other approaches, such as (note some of the following terms are my own invention, since I don't know of standard names for these techniques):

  1. Putt-putt-wait: If the goal is to have a signal that's N times the input frequency, arrange for the oscillator frequency to be at least N times the input frequency; let the oscillator run for N pulses, stop it until the next input pulse, run for N pulses, stop until next input, etc.
  2. Putt-putt-skip: If the goal is to have a signal that's N times the input frequency, arrange for the oscillator frequency to be at least N times the input frequency; allow N pulses of the oscillator through, then stifle pulses from the oscillator until the next input pulse, then let another N pulses through, etc.
  3. Fractional-rate division: If the goal is to have a signal that's N times the input frequency, arrange for the oscillator frequency to be at least N times the input frequency, and provide hardware to stifle a programmable fraction of the oscillator pulses. Either hardware or software may then adjust what fraction of the oscillator pulses are dropped so as to maintain a consistent phase relationship with the reference wave.
  4. Rate-control dithering: If the goal is to have a signal that's N times the input frequency, allow the oscillator frequency be instantly switchable between a rate that's too fast and one that's too slow, and provide hardware to make a programmable fraction of the cycles be "slow" ones. As above, software or software could adjust this fraction so as to maintain a phase lock if desired.

All of these approaches would have the restriction that the oscillator rate has to be guaranteed to be slow enough not to violate the device's internal cycle timings, but I would expect that in many cases they would make it practical to keep a precise counter/timing reference alive even during sleep mode.

What advantages or disadvantages are there to using approaches like the above in lieu of a PLL? I've never seen the latter two approaches used, but I would think that in many cases they'd provide adequate performance while using a fraction of the power of a PLL (perhaps some "digital PLL"'s use approach #3, but I've never heard of such things operating in sub-mA range)

  • \$\begingroup\$ aren't putt-putt-wait and putt-putt-skip the same thing? \$\endgroup\$
    – user253751
    Sep 21, 2020 at 17:40
  • \$\begingroup\$ @user253751: Suppose the reference frequency is 1MHz (period 1us), the target is 10MHz (target 100ns), and the generated period is 98ns. Using putt-putt wait, one would have groups of nine pulses of 98ns each followed by one of 118ns. Using putt-putt skip, every output pulse would be either 98ns or 196ns. Putt-putt-wait would yield a cleaner output, but would require the ability to stall and restart the oscillator cleanly. \$\endgroup\$
    – supercat
    Sep 21, 2020 at 20:48

3 Answers 3


These methods are used. The TI MSP430, for example, uses something they call a "modulator" which is essentially what you're talking about.

The main advantage is that that they are super simple and they can change their output frequency quickly (without any lock-time or whatever that PLL's require), and without any "glitches".

I'll also mention another method that you didn't mention (directly). It is, essentially, a super simple version of making your approaches 3 and 4. It's called a numerically controlled oscillator. Here's a code snippet in VHDL (but it's generic enough that most should be able to follow):

signal phase :std_logic_vector (n_bits-1 downto 0) := (others=>'0');

process (clk_in)
  if rising_edge(clk_in) then
    phase <= phase + inc;
  end if;
end process;

clk_out <= phase(phase'high);

Basically, we have an n_bit long accumulator (a.k.a. counter). On each clock, we add 'inc' to the accumulator. The most-significant-bit of the accumulator is output as the new clock signal. The output frequency is calculated like this:

Fout = Fclk_in * inc/(2^n_bits)

Where Fclk_in is the input clock frequency, inc is the value added to the accumulator, etc. Fout can be anything less than Fclk/2. For more accuracy, or a lower output frequency, you need more n_bits.

The output of this logic is essentially a jittery clock, where the jitter is about 1 clk_in period. The frequency and duty cycle will be dead-on (given n_bits and the clk_in period).

I have frequently used this logic to generate baud rates and other slow but accurate clocks. Since I work with FPGA's and not too many ASIC's I normally keep the logic synchronous with respect to clk_in and output a clock enable signal or something-- but the same concepts apply.

  • \$\begingroup\$ I've used phase accumulators; they can be nice. They have jitter of +/- half an input cycle, as compare with +/- a full cycle jitter one gets from some simpler frequency multiplying schemes. On the other hand, I would expect some other schemes could be implemented in such a way as to use less current. \$\endgroup\$
    – supercat
    Sep 7, 2011 at 4:11
  • \$\begingroup\$ @supercap Yup. +/- half an input clock is "about 1 clk_in period" peak to peak. \$\endgroup\$
    – user3624
    Sep 7, 2011 at 12:36
  • \$\begingroup\$ Yup. And a 4089-style multiplier is 2 clk_in periods peak to peak, but has simpler circuitry, only a small amount of which has to operate on an average cycle. \$\endgroup\$
    – supercat
    Sep 7, 2011 at 14:42
  • \$\begingroup\$ Does the TMS430 lock its clock to a multiple of the input crystal rate? I was thinking about fractional-frequency-multiplication while driving home from work, and "closing the loop" in hardware would actually seem like it could be easier than doing it in software (e.g. if one is trying to generate 1,048,576Hz from a 32KHz source, given a source that's somewhere between 1.050MHz-1.5MHz, one would only need a 4-bit frequency control register; to achieve anything resembling software phase lock without waking a CPU constantly would require finer control). \$\endgroup\$
    – supercat
    Sep 7, 2011 at 14:54
  • \$\begingroup\$ @supercat No it doesn't. It's "clock modulator" is mainly used for dividing down the clock, not multiplying it. \$\endgroup\$
    – user3624
    Sep 7, 2011 at 17:32

First lets look at solutions 1 to 3:

Taking into account that one can make PLL in which vast majority of power (it could be in order of the 90%) is taken by oscillator and divider and the fact that OP solution would always contain those too, the difference in power consumption should not be that big.

Further if you note that PLL oscillator would be working at N times frequency and the OP solutions would always work at bigger then N times frequency the bigger power consumption of the OP solution oscillator can compensate or be even bigger the PLL overhead (last 10%).

So in terms of power there can be no much difference.

The difference will be in size (the OP solution would be for sure smaller if implemented in silicon, non that much difference on PCB with discrete elements) and lock time (OP solution should produce desired output frequency much faster) but also in clock quality (PLL output will be way better).

Now if you consider that clock quality is important in most cases PLL will be used in those. In those rare cases when clock can be lower quality one, that kind of hacks can be and are used.

Second lets look at solution 4:

This is in fact digital PLL (usually sigma delta modulation is used to control oscillator). It is widely used in industry. It has its strong and week points compared to other types of PLLs but it is a PLL anyway.

  • \$\begingroup\$ A conventional PLL from my understanding requires an oscillator design whose frequency behaves somewhat nicely with regard to a high-impedance input voltage; I was under the impression that some of the lower-current oscillator designs were not as amenable to having their frequency controlled via external voltage. \$\endgroup\$
    – supercat
    Sep 7, 2011 at 12:42
  • \$\begingroup\$ Incidentally, I can mention a situation where I've seen both putt-putt-wait and putt-putt-skip used in practice: video-overlay generation (gated off HSYNC). If one has an oscillator that's amenable to putt-putt-wait, that can be a nice easy approach to roughly placing monochrome video content on the screen. If one has a fast enough oscillator (over 16MHz or so) using putt-putt-skip may not yield results quite as clean as those from a proper PLL, but much easier than using a PLL and it's often good enough. \$\endgroup\$
    – supercat
    Sep 8, 2011 at 18:30

It is worth noting that PLLs are frequently used to obtain frequencies that are difficult to get from a normal (quartz) oscillator. They do this and still maintaining good frequency accuracy (needed for i.e. radio transmissions).

When dividing a high-frequency clock people get more creative but phase accumulators (as described by David) seem most popular. I believe they are used in all DDSs and also in some UARTs (for fractional baudrate division).


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