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I need some help with the following circuit: Circuit

I simulate it using LTSpice IV and have this:

Simulation

But I couldn't get that thinking. Of course, I know that it's possible that there's some DC voltage before the capacitor C2 if it's Ground on the other side, but I couldn't get that.

For example, I thought that, in Vnode, it had to be something like the characteristic curve of a capacitor discharging in a AC voltage.

Any help will be appreciated. Thanks!

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  • \$\begingroup\$ One common name for this circuit is "half-wave voltage doubler". If you search that in google books you may find more or less intuitive explanations how it works. Here is one. \$\endgroup\$ – Fizz Sep 23 '15 at 1:48
  • \$\begingroup\$ Also, if you set C1 to a [much] smaller capacitance value than C2 you should be able to see in simulation how C2's voltage gets pumped up over several cycles, which explains the alternative names for this circuit ("diode pump" or "charge pump"). \$\endgroup\$ – Fizz Sep 23 '15 at 2:04
  • \$\begingroup\$ Another way to think about this circuit is to break it down in two stages, the clamp (C1 and D2 in your diagram) and the rectifier. Marston's book on diodes etc. has an explanation along these lines, although you need to read a few pages (pp. 13-23) to get all that info. \$\endgroup\$ – Fizz Sep 23 '15 at 2:30
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I think you will see more interesting signals if you set your transient analysis so you can observe the initial milliseconds of your circuit. It looks like you set "Time to start saving data"=0.9. Set it to 0 and change the "stop time" to 0.2 (you will see the first 10 cycles) and you will realize what is going on. You can access these parameters by right clicking over the .tran statement in LTSpice. Good luck!

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This is a charge pump. It works by literally pumping charge like a water pump would pump water. Those capacitors will not have an RC discharge characteristic because there are no 'R's in the circuit.

Use this as a thought experiment to understand what's going on: Imagine the capacitors are flexible membranes, and the diodes are 1-way valves (ignore Vf for now). That should make it clear why the circuit behaves the way it does.

Edit: Ok, here. This simulation has all of the voltages and currents, and simplifies things by using a square wave instead of a sine wave. You need to pay attention to the current in the circuit to understand what is going on.

schematic

simulate this circuit – Schematic created using CircuitLab

Voltages Currents

This circuit will behave in a more complex way if there is a load resistor across C2, because in this case, after the first cycle, C2 becomes completely charged and nothing else happens.

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  • \$\begingroup\$ That's true, I don't have any resistor to discharge. But this is the first time I see a capacitor behaving like this and I don't understand that, thinking in the way you are doing it. \$\endgroup\$ – Unnamed Sep 21 '15 at 22:55
  • \$\begingroup\$ Think of V1 as a piston pushing and pulling on water in a pipe. C1 is a membrane, so no water flows through it, but it pushes and pulls an equal amount of water on the other side. Water only goes one way through the diodes in the direction of the arrow. \$\endgroup\$ – Daniel Sep 22 '15 at 4:17
  • \$\begingroup\$ In the 'push' phase, water (current) gets pushed through D1. During the 'pull' phase, D1 gets blocked and more water (current) is pulled in through D2. \$\endgroup\$ – Daniel Sep 22 '15 at 4:20
  • \$\begingroup\$ Once the voltage across C2 (Vout) is at its maximum, the pump doesn't actually push current through D1 anymore, so Vout steadies at its maximum value. \$\endgroup\$ – Daniel Sep 22 '15 at 4:21
  • \$\begingroup\$ Sorry Daniel, but I don't understand. Is there any textbook where I can read this? Or any video in youtube? \$\endgroup\$ – Unnamed Sep 22 '15 at 4:42
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You are doing something wrong/counterproductive in your simulation and (per Arcu's observation) that's your tran command. Even with equal capacitors, I have no trouble seeing the initial charging before it transitions to steady state.

As per my comments, Vd looks exactly like a clamp. enter image description here

And (also per my comments) the charging action of C2 is even more evident if you lower C1 as done below. It now takes many more cycles for the output to reach the ~18V value.

enter image description here

Also you say

I thought that, in Vnode, it had to be something like the characteristic curve of a capacitor discharging in a AC voltage.

It's not clear to me what you mean by that exactly, but the first diode and capacitor form a so-called clamp; once steady state is reached, the clamp shifts the sine wave (or any other waveform) so that the its bottom peaks (in this case) are aligned with the 0V (minus a diode forward drop actually). This is exactly what we see with Vnode/Vd in simulation. The graphics on Wikipedia are actually incorrect (as noted on the talk page there for some years) with respect to the transitional phase; the clamper does clip the output voltage (as seen in my simulations) so it doesn't go below approx -0.6V (the diode junction voltage drop) during the transition.

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