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I'm thinking of a very simple circuit to generate high voltage pulses, like this:

schematic

simulate this circuit – Schematic created using CircuitLab

The MOSFET in this case will turn on until the current through L1 ramps up to 10A, then turn off. The pulse output is connected to a load which can have a wide range of impedances. If the impedance is low, then the energy in L1 goes there. If the impedance is high (higher than 600V / 10A = 60 ohm), then the 600V Vds on the MOSFET can be exceeded. If I understand correctly, that means it will go into avalanche, and conduct until the current goes below some kind of threshold (or the voltage drops??). This MOSFET happens to be rated for repetitive avalanche energy of 41.7mJ, and avalanche current of 47A. The energy in L1 is (1/2) * 6uH * (10A)**2 = 0.3mJ which is much less than the rated energy.

Is this something that the MOSFET can survive? (Let's say pulses at 10kHz, repeated indefinitely) I've never used a MOSFET in this way, it seems like it would stress the device a lot.

When does a MOSFET in avalanche mode turn off? Is there a way to make it turn off?

What is Vds during avalanche?

P.S. It is possible to limit the peak pulse voltage to less than 600V using some kind of RC pulse shaping network, or zeners or TVS diodes, but that makes things more complicated and is not preferable in my case.

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  • \$\begingroup\$ Did you work out the power dissipation? I am not sure to what extent the avalanche activity will damage the MOSFET, but the max junction temperature would still need to be respected. 0.3 mJ * 10,000 pps = 3 Watts, if I didn't make a mistake. You also need to account for the dissipation caused by Rds * Id^2 during the inductor charge period. \$\endgroup\$ – mkeith Sep 22 '15 at 1:58
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    \$\begingroup\$ @mkeith: Yup, I got 3W also, that seems quite manageable for this device. L1 goes from 0 to 10A in 6uH * 10A / 48V = 1.25us, power dissipation = (1/2) * 1.25us * (10A)**2 * 73 milliohm Rds * 10kHz = ~0.045W. Some energy would also be dissipated during the transition from off to on, but not enough to be much of a problem. \$\endgroup\$ – Alex I Sep 22 '15 at 2:50
  • \$\begingroup\$ Cool concept. I like interesting uses like this. Have you considered individual breakdowns, like drain-gate? What do you plan on attaching to the gate? \$\endgroup\$ – curtis Sep 22 '15 at 4:58
  • \$\begingroup\$ @curtis: Thanks! The plan is to use MIC4452 or UCC37322 gate driver IC, running from a 12V supply. I might add some back-to-back zeners to clamp the voltage at 18V or so. I haven't thought about drain-gate, could you explain about that? There is no value for it in the datasheet. \$\endgroup\$ – Alex I Sep 22 '15 at 5:16
  • \$\begingroup\$ I should of done some homework before asking questions. I was thinking in terms of a traditional FET. Apparently, power FETs are often lateral devices with VdgBD similar to VdsBD. Since you'll have some resistance on the gate and Vgs leakage is minimal up to 30V, VgdBD is not a limiting factor. I'm assuming that's why they don't bother with it on the datasheet. Hopefully, someone else will chime in with more knowledge specific to power FETs. \$\endgroup\$ – curtis Sep 22 '15 at 17:56

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