In a previous question where a SMPS based on an LM5118 was presented, some aspects of the layout were pointed out as being problematic. I've taken another look at the layout of that section of the board and in light of the advice given, the IC datasheet and reference design, I've made some modifications to the layout with the aim of resolving any layout issues.
Here's the top side:
Bottom side (as viewed from top):
Schematic page 1:
Schematic page 2:
Things I've tried to keep in mind:
- I've tried to keep the bottom layer continuous underneath the high current loops so that the return currents can travel along the bottom layer, directly beneath the top layer, thus minimising the loop area.
- Separate ground area for the analogue section of the SMPS, connecting directly to the AGND pin.
- Solid ground plane between PGND pins, input and output caps.
- Gate signal for Q2 rerouted to move it away from the inductor and to try and improve its loop area.
I appreciate that other parts of the circuit (not shown) can have an effect on the layout as well, but if the SMPS section is considered separately, I was wondering what feedback people can give regarding the layout, and if there are any issues or improvements that could be made.