In a previous question where a SMPS based on an LM5118 was presented, some aspects of the layout were pointed out as being problematic. I've taken another look at the layout of that section of the board and in light of the advice given, the IC datasheet and reference design, I've made some modifications to the layout with the aim of resolving any layout issues.

Here's the top side:

Top Layer

Bottom side (as viewed from top):

Bottom side

Schematic page 1:

Schematic 1

Schematic page 2:

Schematic 2

Things I've tried to keep in mind:

  • I've tried to keep the bottom layer continuous underneath the high current loops so that the return currents can travel along the bottom layer, directly beneath the top layer, thus minimising the loop area.
  • Separate ground area for the analogue section of the SMPS, connecting directly to the AGND pin.
  • Solid ground plane between PGND pins, input and output caps.
  • Gate signal for Q2 rerouted to move it away from the inductor and to try and improve its loop area.

I appreciate that other parts of the circuit (not shown) can have an effect on the layout as well, but if the SMPS section is considered separately, I was wondering what feedback people can give regarding the layout, and if there are any issues or improvements that could be made.

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    \$\begingroup\$ One comment is that you should add thermal relief to components on polygon pour. You or the assembler may have a hard time soldering components on polygon pour because it will act as a heat sink. \$\endgroup\$ – efox29 Sep 22 '15 at 21:08
  • \$\begingroup\$ @efox29 Thanks for the suggestion - I'm guessing that really only applies to through hole/hand soldered components (there are a few on there that would benefit from thermal relief) \$\endgroup\$ – Amr Bekhit Sep 22 '15 at 21:09
  • \$\begingroup\$ The thermal relief for SMD may also be required for future repairs/mods. \$\endgroup\$ – BenG Sep 22 '15 at 22:20
  • \$\begingroup\$ What is the via between U1 and C22 for? If it's leading to the power plane, that's not how I'd recommend doing it. You want the power (loosely used term here) to go from the plane to the capacitor to the chip. In other words, the cap should be between the source and the power pin of the chip. Otherwise it may not decouple the chip very well. \$\endgroup\$ – DerStrom8 Sep 23 '15 at 12:23
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    \$\begingroup\$ @derstrom8 Sorry I misunderstood which via you meant! I know which one you mean now, just to the right of C22. Yes I see your point there, well spotted. \$\endgroup\$ – Amr Bekhit Sep 23 '15 at 13:01

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