Can someone explain me how this parallel binary counter works: enter image description here

For example, if the state in the beginning is 0000, what happens when Pt goes high?

  • \$\begingroup\$ I edited the post, uploaded wrong picture. \$\endgroup\$ – A6SE Sep 24 '15 at 21:08
  • \$\begingroup\$ If this is homework, we don't provide solutions or even hints before you've shown some work. What do you think happens? \$\endgroup\$ – tcrosley Sep 24 '15 at 21:28
  • \$\begingroup\$ No, not homework, I'm skimming through my scripts and ran across this. What bothers me is, does flip-flop A ever change state? What I think happens here (which looks completely wrong) is: if all flip-flops are in state 0, then, when Pt goes high, the states change to 0111, but that doesn't make any sense.. I'm really confused here and I think there's just a detail I'm missing... \$\endgroup\$ – A6SE Sep 24 '15 at 21:34

Assuming there is a common clock connected to all of the T flip-flops here what will happen when Pt is high:
The T input of the A FF will be 0, so the output (A) will not change, i.e. will be constantly A=0. As it is connected to the NANDs, their output will be always 1, so B, C and D will flip every clock. So it will be like 0000, 0111, 0000, 0111.. Which is not a counter at all.

If Pt is 0, the outputs of all of the NANDs are going to be 1, so each FF is going to flip every clock cycle. So it becomes like 0000, 1111, 0000... Which doesn't make sense as counter as well. So we can conclude that you have a mistake in your drawing. The correct one would be if we replace the NAND gates with AND like here: enter image description here

** The image is taken from here.


Here is an example actually using T flip-flops like the ones in the question. You'll notice the flip-flops in the example do not have CLK inputs like most do, instead they are like the ones described here, i.e. they clock on every positive edge of the T input. Also, the gate feeding the inputs of each T-flip flop is a NAND, rather than AND, so the flipflops will gate at the falling edge of Pt, not the beginning.

Here is a diagram of what happens:

enter image description here

The A flip-flop toggles on the end of every Pt clock, since it has essentially just a inverter feeding the T\$_{A}\$ input. So it first toggles from 0 to a count of 1. I have shown the counts vertically for each state, so 1 0 0 0 = top to bottom is 1 (Q\$_{A}\$ shown at top, Q\$_{D}\$ at bottom).

On the second clock pulse, when Pt is high and Q\$_{A}\$ is high, this causes the T\$_{B}\$ input to go low (because for a NAND gate, if both inputs are high, the output is low). This is shown by the first vertical red line in the diagram. T\$_{B}\$ goes back high when Pt goes low, and this positive edge transition toggles B and Q\$_{B}\$ is now high.

The same thing happens for flip-flop C, two more Pt pulses down the road. Here both flip-flop B and C toggle, the latter since Pt, Q\$_{A}\$ and Q\$_{B}\$ are all high (see second red line, terminating at T\$_{C}\$). This corresponds to the three-input NAND gate feeding T\$_{C}\$.

Although I haven't shown it, the same thing will take place when the count goes from 1 1 1 0 to 0 0 0 1, Pt, Q\$_{A}\$, Q\$_{B}\$, and Q\$_{C}\$ are all high which will cause flip-flop D to toggle.


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