The short answer to why are the high side FETs heating up (as already given by I Chodera) is switching loss due to insufficient gate drive. But, let's use some Baby Math to give a rough analysis of what that means.
Gate Drive:
Not only are the high side FETs hot, but the IR2110 should be pretty toasty too, driving all those FETs. Power lost in the gate circuit, and that will be mostly in the IR2110, is:
\$P_{\text{Gate}}\$ = \$V_{\text{drv}} f_{\text{pwm}} Q_g\$ = (12V)(50kHz)(6)(150nC) ~ 0.5W
Since the thermal resistance of the IR2110 is ~ 100C/W, it will have a temperature rise above ambient of ~50C. Let's say ambient is 50C, so that junction temp is 100C. Who cares? Well, \$R_o\$ (output resistance) of the IR2110 is ~8Ohms at 25C, but it is a MOS device, so resistances at 100C are about 1.5 times those at 25C. With a heat elevated \$R_o\$ of ~12Ohms (plus about 3Ohms of additional gate circuit resistance), the IR2110 will not be driving as hard as you think.
Switching Loss:
Most of the switching action in a topology like this takes place while the gate drive processes the Miller plateau charge (\$Q_{\text{mp}}\$). Normally the rising and falling times (\$\tau \$) are different, but here they will be equal (and later combined, 2 \$\tau \$) because, Baby Math. So, the FETs switching time is going to be:
\$\tau \$ ~ \$\frac{2 R_g Q_{\text{mp}}}{V_{\text{drv}}}\$ = \$\frac{2 \text{(15 Ohms)(6)(75 nC)}}{\text{10V}}\$ ~ 1.4uSec
For the loss calculation, peak inductor current will be used as a simplification.
\$P_{\text{sw}}\$ = \$I_{\text{pk} } \tau V_{\text{ds}} f_{\text{pwm}}\$ = \$\text{(24V)} \text{(9A)} \text{(1.4uSec)} \text{(50kHz)}\$ ~ 15W
From the equations you can see that reducing the loss could be accomplished by:
- Improving the gate drive.
- Use fewer FETs, another way to reduce \$\tau\$.
- Lowering the switching frequency.
If 100W is all the power to be processed, it makes no sense to have 6 parallel power modulators. One would do.
A good reference for loss in Synchronous Bucks is Fairchild AN6005.