# How to terminate switching transistor for level change?

For a typical driver, I would add a series termination resistor to terminate the line.

But what would be the correct way to terminate when a transistor is used to level shift a 3.3V/5V signal to some arbitrary voltage ?

Consider a simple circuit, V1 is some higher voltage to which I am switching to. Could be 12V, 15V, or 30V. R2 is a pullup. The pullup value would be most likely greater than Z0, otherwise, the power loss at high frequencies could be pretty big. 30V and say R2 is 50 ohms, thats 18W, when the transistor turns on and 600mA through it. So I would imagine that that the pullup would be much higher to combat that.

• IIRC, the first chapters of Johnson & Graham talk a lot about how logic designers in the early 80's neglected transmission line effects, and it worked perfectly fine until their chips got fast enough to need it. For a 1 MHz signal, you should be able to get away with it too, unless you're driving a particularly long long. – The Photon Oct 1 '15 at 3:10

You have a few choices.

1. Make $R_2=Z_0$. This does consume more power, but it is essentially how a CML driver works. (CML reduces the logic swing to 1.0 V or less to mitigate this).

2. Add an RC circuit in parallel with R2 to make the line match at high frequencies, while keeping the low static power dissipation when the output is low.

3. Don't match at all. With 1 MHz fundamental, the wavelength is 300 m. Even if you take the 10th harmonic, that's 30 m, so if the length of the line is less than 3 m, your system is likely to work well without matching.

A simple common-drain inverter like you have drawn typically doesn't have particularly fast edges, so you may not even need to worry about so many harmonics, and you may be able to get away with not matching for longer paths. The rising edge is easy to slow down, simply by making R2 larger. To keep the falling edge slow as well, you might add a series resistor at the output, or deliberately slow down the signal reaching the gate of the FET.

With such high pull-up the slew rate will be slow enough that you don't need to worry about the low to high case. For the high to low case you have a common situation so just terminate with a series resistor so that the transistor resistance plus the series termination equals Z0 (50 ohm in your example).

Since you don't want to dissipate the power in the resistor you are probably not worried about speed.

If you do want the speed then you could put a buffer (such as complementary emitter follower) and the 50 ohm series termination. The static power would then be zero but you would get the fast transitions.

According to simulation results, traditional matched source termination seems to work just fine. I also can't think of anything wrong with matched termination on the other side of the transmission line (i.e. in parallel with R2), however keep in mind that the steady-state voltage will be quite low if R1 is large compared to the termination at low frequencies. Furthermore, Trying to impedance match only R1 doesn't work because it doesn't properly terminate M1. Note that the capacitance of the IRF530 is being RC filtered heavily on one edge because of R1. Picking a mosfet with lower capacitance reduces this filtering.

As The Photon stated, 1MHz has a long wavelength so you may not even need to match the impedance.

Matched Source termination: works just fine

Unmatched Source termination: lots of reflections

Trying to match source termination with R1: lots of reflections

• This is good. I didn't know LTSPICE can sim transmission lines. How did you get your model to run ? I pretty much copied yours, and I have a floating node with the transmission line even though, every node has a valid connection – efox29 Oct 1 '15 at 4:13
• It seems my version of LTSPICE connects the ground node on each side smartly. You could try manually adding the ground node on each side. – helloworld922 Oct 1 '15 at 4:21
• Ya, thats what I ended up doing. Got it now. Thanks! – efox29 Oct 1 '15 at 4:22