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I am currently trying to design a circuit that needs a large frequency division, 25353 to be exact. I'm aware that I could do a large complex flip flop arrangement to achieve close to the desired results, but I'm guessing there is a more elegant approach that I am unaware of. Maybe an IC that does this? I found an SN54LS294 from TI that has up to 215 programmable frequency division.

Any advice would be great. I have to do this large division due to limitations in part availability, etc.

EDIT:

I am trying to take a 57.5 MHz digital signal and convert it down to 2.268 kHz (~ 25353 division). I'm trying to accomplish this with a digital divider. I have found the IC mentioned above that I can use to get a frequency of around 3.5 kHz (214 division) or 1.755 kHz (215). If I take the 214 approach, I can then divide by another 1.5 to get very close to the desired frequency. I understand that this is fairly trivial, but I am new to frequency division. Currently researching the divide by 1.5 thing.

EDIT:

After following WhatRoughBeast's instructions, this is the circuit I have come up with. I am trying to divide by about 20,723 (now converting 47MHz to 2.268KHz). If I first divide by 8 to get my 47MHz signal down to a lower level, this would leave 2590 for the other three dividers. Subtract 1 for the clock reset, and I need to divide by 2589 or 1010 0001 1101. Invert that word to get 0101 1110 0010 and use that logic on the presets.

Here is the circuit:

CircuitLab Schematic 6u368b

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    \$\begingroup\$ So what nice big numbers divide into it. Have you found any yet. Not hard but it's nice to see someone having a go at some leg work. Like this 7x7x7x71 \$\endgroup\$
    – Andy aka
    Commented Oct 1, 2015 at 17:04
  • \$\begingroup\$ What is the signal frequency or frequency range? Also, is this a digital signal? If not, tell us all about it (amplitude, is it a sine wave, etc). \$\endgroup\$
    – user57037
    Commented Oct 1, 2015 at 17:12
  • \$\begingroup\$ Updated the post with more info. Also had the wrong division number, correct is 25353. \$\endgroup\$
    – jareddbh
    Commented Oct 1, 2015 at 17:39
  • \$\begingroup\$ Are you making a PCB for this, or is it a one-off hand-built prototype? \$\endgroup\$
    – user1844
    Commented Oct 14, 2015 at 16:50
  • \$\begingroup\$ It's going to go on a PCB, but it will be just for demo purposes. \$\endgroup\$
    – jareddbh
    Commented Oct 14, 2015 at 17:44

4 Answers 4

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A 57.5 MHz clock frequency is going to be a challenge for you. First, you will have to take your clock and run it through a high-speed comparator to give you a signal of about 0 to 5 volts. Fortunately, this doesn't have to drive a terminated line as long as the load line is less than, let's say, 1 foot.

For this frequency, a 74HC4040 will simply not work. It's only guaranteed to work to 30 MHz, and for this sort of thing you do not want to depend on "typical" numbers, even though the data sheet gives this as 82 MHz.

What you can do is provide a 2-step function, using a prescaler to drop the clock frequency to something more convenient. Along this lines, you should analyze your divider ratio in terms of the accuracy you actually need, and work within that range, rather than taking your nominal ratio as set in stone.

In your case, for instance, if you go to a divider ratio of 25352 (which will give a nominal output of 2268.02 Hz - close enough?) this equals 8 times 3167. You can use a high-speed counter such as a 74AC161 as a divide-by-8, which will then feed a slower, longer divider which handles the 3167 part. It can do this since $$\frac{57.5 MHz}{8} = 7.19 MHz$$ and this is well within comfortable limits.

Secondly, DO NOT TRY TO USE A 4040 for the long divider. 4040s are very useful as a compact source of factor of 2 division. For this usage, a 4040 of any family is a truly horrible choice and a disaster waiting to happen unless you really know what you're doing - and with all due respect you don't. For a divider ratio in the range of 2049 to 4095 I would not recommend trying to use it at a frequency of more than about 4 MHz with a tricky design and not more than 2 MHz for a relatively simple design. The problem is that a 12-bit count will need about 240 nsec maximum to complete the count, and during this period will provide false values to the reset circuitry. Depending on the exact divisor selected you'll either get a stable wrong division ratio or a weird, inconsistent mish-mash of wrong ratios. Neither is good.

The following circuit ought to work. It uses 5 ICs and is about as compact as you'll get.

schematic

simulate this circuit – Schematic created using CircuitLab

EDIT It is also possible to do away with a separate decoder, but not an external gate. This will take a little bit of thinking. Let's start with a single 4-bit presettable counter such as the 74HC161/163. The general connection is

schematic

simulate this circuit and the question is, what should happen to the presets? Note that when the counter reaches 1111 (15 in binary), the next clock will preset it. So, let's say that you want to create a divide by 3. If you preset to 13, the count sequence will be 13,14,15 (issue preset), 13,14, etc. The preset code will then be 1101. Now, here's the trick. If you take 3 (the desired ratio), and subtract 1, you will get 2. The binary code for 2 is 0010. If you invert each bit, you'll get 1101, which is the desired preset code.

So the rule for calculating preset values is 1) find the desired division ratio, 2) subtract 1, 3) invert all bits. Oh, and then there's 4) determine the largest bit which toggles, and use that as your divider output. Here the rule is, find the leftmost (most significant) bit in the binary ratio which is set to zero, and use that. So in the case of a divide by 3, you would use QB out of the counter.

The reason that you need the inverter is that the toggle carry is active high, but the load input is active low. There are some counters, such as the 74HC/AC191, 169 and 669 which have an active low TC output, and you can look into them if you like.

For dividers with more than 4 bits, you just connect each TC output to the ET output of the next stage.

For your use the circuit will look like

schematic

simulate this circuit and I will leave the calculation of the preset inputs up to you.

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  • \$\begingroup\$ I was just going to add to any of these answers (but is most touched-on here), beware of latency if cascading gates. If the output of this divider must exactly line up with the reference frequency, it will be delayed by each element of the divider. Simple solution is to introduce similar-delay elements on the reference signal, so that both are delayed equally. Then feed both to the rest of the circuitry. \$\endgroup\$
    – rdtsc
    Commented Oct 2, 2015 at 0:26
  • \$\begingroup\$ @rdtsc - Or you can do what I've done: first, the 3 counters on the right, which provide the 3167 division, are all fed from the same clock, so there is no ripple unlike the 4040, and the reset mechanism is also using a synchronous load function, rather than an asynchronous reset (the MR pin). \$\endgroup\$ Commented Oct 2, 2015 at 0:32
  • \$\begingroup\$ Accepted answer, thank you Beast! Also, that CircuitLab link is great! I've since switched to a 42 MHz to 52 MHz source, so I'll play around with your circuit to get the new division. \$\endgroup\$
    – jareddbh
    Commented Oct 9, 2015 at 16:44
  • \$\begingroup\$ I have a simple question about the division shown in this circuit. There is an initial divide by 8 with the 74AC to provide the clock to the rest of the chips. Then it looks like there is a divide by 111000100110 (3622)? I think I may be reading the MSB and LSB incorrectly. I'm confused on how that is providing 3167 division. \$\endgroup\$
    – jareddbh
    Commented Oct 12, 2015 at 16:00
  • \$\begingroup\$ @jareddbh - Well, the schematic is indeed in error, but not what you think. You're reading them in the wrong order. lsbs are on the left IC, msbs on the right. So the reset code as shown is 0110 0010 1110 or 3118. I've edited the schematic, and the code is now 0110 0101 1110, or 3166. Since a reset sets the counter to zero rather than 1, the total period will be 3167 counts. My apologies for the error. \$\endgroup\$ Commented Oct 12, 2015 at 17:05
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You can easily cascade devices such as the 74HC163 to do any division ratio. That would take 4 chips. (The 160,161,162 and 169 are similar with slightly different features)

If using the 74163 you set the 2's complement of the division ratio at the preset inputs to the counters since it counts up. With a count down you would set the division ratio directly. When the terminal count is reached (all 1's for the 74161) the start count is preloaded - no external gates are needed for this. So you would need just 4 chips.

The 74163 family have a useful method of cascading that doesn't require any additional components or slow down their operation.

Each chip that counts 4-bits has a fast Ripple Carry Output that is used to enable the next most significant stages of the counter. It effectively gives 16 times as long for the logic to settle and thus increases the maximum counting speed.

Cascaded modulo-n counter using 74163

A useful lecture on counters See page 26.

Edit

For a frequency of 57MHz you will need one of the faster variants of the 74163 such as the 74AC163 (or the 74AC161). They will operate at over 100MHz.

Edit

After a discussion with WhatRoughBeast it looks like even the fastest variants of the '163 like devices can't do 57MHz in one stage.

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  • \$\begingroup\$ A simple 4-stage divider using 74HC163s as counters, a 74HC30 as a count detector, and 5 volts power supply will have a max guaranteed clock frequency of about 8 MHz. This counts counter propagation delays, setup times for carries and reset, and propagation delay through the gate. It may do much better than this, but it may not. A more sophisticated carry scheme will allow about 15 MHz operation (guaranteed). \$\endgroup\$ Commented Oct 2, 2015 at 15:09
  • \$\begingroup\$ @WhatRoughBeast - You don't need the 74HC30 as you can use the preload feature of the counter. The AC versions of the '161 can run at >100MHz. \$\endgroup\$ Commented Oct 2, 2015 at 23:53
  • \$\begingroup\$ True about preload, but the poster has no idea how to determine the preload bits. And while the AC may have an individual 100 MHz+ clock rate, the delays for ripple carry will give a 4-chip counter a considerably lower speed. I make it about 36 MHz for simple ripple carry and 5 volts. Propagation CP to RC, 2 TE to RC, and setup of last TE input totals 27.5 nsec. \$\endgroup\$ Commented Oct 3, 2015 at 0:18
  • \$\begingroup\$ True 100MHz is a stretch but with the fast carry configuration it is CP to TC + PE to CP setup = 11.5 + 1 = 12.5ns = 80MHz. The propagation of the carry can take 15 clocks. These are On Semi parts @5V over temperature. \$\endgroup\$ Commented Oct 3, 2015 at 0:38
  • \$\begingroup\$ Actually, you misread the data sheet. 1 nsec is PE hold time. Setup is 8.5 nsec, so absolute best counter frequency is 50 MHz. And I really doubt the poster understands the fast carry issue. \$\endgroup\$ Commented Oct 3, 2015 at 0:58
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If the frequency of the input signal is low enough (up to 50 MHz or so) that you can use standard logic, you could make ANY division factor by cascading one or more 74HC4040 ICs.

How to count to a certain number ? As you know decimal 10 is binary 1010 So you AND outputs Q0 and Q1 and with that RESET the counter. Now the 4040 will count to 10 and reset.

If you want decimal 11 this is binary 1011 So you do RESET = Q0 AND Q1 AND Q3

The 4040 is a 12 stage binary counter, cascade 2 of them and you can count up to 24 bits which is about 16.7 Million.

You have a large number which is not a multiple of 2 so that that will be a large AND function ;-)

Edit: there's an issue with resetting like this, see other answer.

Edit: You would like to divide by 1.5 Dividing by 1.5 is possible but there are some caveats ! A standard divide by 2 can work by toggeling the output on the rising slope of the input signal. You can make a divide by 1.5 by using both the rising and the falling edge of the input signal. The output would then need to toggle in a 1 - 2 - 1 - 2 ... fashion:

schematic

simulate this circuit – Schematic created using CircuitLab

If you want a PRECISE frequency division, for example 3.1415 ( 3 1415/10000) that is possible with a fractional divider. Actually, the divide by 1.5 I mentioned above is the simplest implementation of a fractional divider. Note how it divides by 1 - 2 - 1 - 2 to arrive on an AVERAGE division ratio of 1.5 :-)

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  • \$\begingroup\$ The input signal is 57.5 MHz +- 5.9% (adjustable 54.11<f<60.89 MHz). The output signal will be adjustable as well, so a linear division is fine. \$\endgroup\$
    – jareddbh
    Commented Oct 1, 2015 at 17:49
  • \$\begingroup\$ OK, for 74HC4040 that would be too close to the edge, but there is also the 74AC4040 which should be able to handle up to 149 MHz so that would do the job. If the 74AC4040 is too expensive you could also make the 2nd counter a 74HC4040 as it will count on a 2^14 times lower frequency. \$\endgroup\$ Commented Oct 1, 2015 at 18:41
  • \$\begingroup\$ Awesome description! Thanks! Going to try your 74HC4040 method. \$\endgroup\$
    – jareddbh
    Commented Oct 1, 2015 at 21:24
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    \$\begingroup\$ @jareddbh - Pay attention to the comment. A 74HC4040 is only guaranteed to work (by itself) to 30 MHz. Adding a set of AND gates will slow this even further. \$\endgroup\$ Commented Oct 1, 2015 at 22:52
  • \$\begingroup\$ Downvoted. Your reset function simply will not work reliably. The 4040 is a ripple counter, and the outputs show significant skew (up to 20 nsec/stage), which will cause false resets for some codes. \$\endgroup\$ Commented Oct 2, 2015 at 2:24
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Did you consider using a 74HCT4059 Divide-By-N counter? We have been using this very useful IC successfully in several designs. NXP still manufactures it. It has several modes of operation and I believe it can solve your design challenge pretty elegantly.

Best regards.

Omer

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    \$\begingroup\$ Can you please give a more direct explanation of how this chip can be integrated to accoplish the OP's stated goals. Welcome to EE.SE & thaks for your helpful first post. :-) \$\endgroup\$ Commented Feb 21, 2016 at 4:50

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