The point is, of course, speed.
There are currently three versions of PCI Express with a fourth version in the works. Version 1 used a serial signalling rate of 2.5GHz. So if a x1-width card/socket were used, the maximum signalling bandwidth is 2.5G * (10 bits for 1 byte) = 250MB/s. 10 bits are signalled for 8 bits of data, so efficiency is 80%. Of course, there are TX and RX pairs of wires for communication in each "width" or "lane" of slot, so a x1 slot has 1 TX and 1 RX path as it's "lane." x2-width slots are seldom seen in my experience. x4 is 4 TX lanes and 4 RX lanes, enabling 250MB/s * 4 = 1GB/s. x8 slot = 2GB/s. x16 slot = 4GB/s.
PCIe v2.0 doubled the signalling rate from 2.5GHz to 5.0GHz, which of course doubles all of the previous bandwidths.
PCIe v3.0 couldn't double the signalling rate, but did bump it up to 8.0GHz. They also changed the specification to include less check-bits, sending 130 bits for 128 data bits, increasing the efficiency to 98.46%. x1 slot = 8.0G * (128bits/130bits) = 985MB/s to x16 slot = 15.754GB/s.
PCIe v4.0 is still being specified, but in 2017, intends to bump the signalling rate up to 16.0GHz, effectively doubling the v3.0 speeds. The encoding scheme hasn't (yet) changed.
Added (to answer refined question):
This link explains why serial links are faster than parallel, and essentially says that parallel links are more greatly affected by cross-talk and propagation delay issues as the clock rates are increased, which limit their speed. Serial links use a "differential" or "opposing-phase" transmission system, where two wires are used for each TX and RX link. The wires are driven with opposite polarity voltages, such that the receiver only needs to detect whether the signals are both one way or the other, which almost eliminates the issues that plagued parallel links. This is why serial links can go into the gigahertz range, and parallel links are much more limited.
And from the aforementioned Wikipedia article, "Data transmitted on multiple-lane links is interleaved, meaning that each successive byte is sent down successive lanes. The PCIe specification refers to this interleaving as data striping. While requiring significant hardware complexity to synchronize (or deskew) the incoming striped data, striping can significantly reduce the latency of the nth byte on a link."
AndrewM has to say, "The answer is that multi-lane serial links stripe bytes across the lanes at the sender and buffer them back into contiguous memory at the receiver (as appropriate). This maintains the resistance to propagation time differences, while increasing bandwidth."
So the data is striped, simultaneously, down all links at the same time. So data is broken up into blocks and sent, in parallel (more or less - receiver's job to synchronize the data), down all of the available links. It is a form of parallelization... just using serial links.