# CMOS: Why is an nMOS transistor a bad conductor of high logic, but a good conductor of low?

I can't find an answer that addresses this and makes sense to me. I know that V_t is subtracted from the 'output', but I don't understand why.

• What is "high logic" and "low logic"? Oct 2, 2015 at 18:50

It's all to do with gate voltages.

A standard Enhancement Mode NMOS requires a positive gate voltage relative to its source. With this in mind, lets look at the following to options:

simulate this circuit – Schematic created using CircuitLab

In the two circuits, lets analyse what happens if we connect $0$ and $V_+$ to the input.

First we will start with $0\mathrm{V}$.

In the circuit on the left, when $0\mathrm{V}$ is applied to the gate, you have a gate voltage, $V_{gs}=V_g-V_s=0-0=0 \mathrm{V}$. This will be below the threshold voltage $V_t$, so the transistor will be off and the output will be pulled high.

In the circuit on the right, when $0\mathrm{V}$ is applied to the gate, you have a gate voltage, $V_{gs}=V_g-V_s=0-0=0 \mathrm{V}$. Again, this will be below the threshold voltage $V_t$, so the transistor will be off - note that the resistor $R$ will pull the source down to $0\mathrm{V}$.

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Now lets try connecting $V+$, lets say for simplicity this is $+5\mathrm{V}$ and the transistor has a threshold voltage of $+2\mathrm{V}$ to conduct.

In the circuit on the left, when $+5\mathrm{V}$ is applied to the gate, you have a gate voltage, $V_{gs}=V_g-V_s=5-0=5 \mathrm{V}$. This is way above our threshold voltage, so the transistor will be turned on, and pull the output down to zero. This is the opposite state of when we apply $0\mathrm{V}$ to the gate, which means we have successfully made an inverter.

Now in the circuit on the right, when we apply $+5\mathrm{V}$ to the gate, we start to turn the transistor on, but by how much? Well, to begin with, we have a gate voltage of $V_{gs}=V_g-V_s=5-0=5 \mathrm{V}$, great, the transistor turns on. BUT, when the transistor turns on, it starts to conduct, which means the output voltage starts to rise. If the output voltage rises, $V_s$ starts to increase, which means our gate voltage goes down.

If this were to go on, eventually we would reach an output voltage of $5\mathrm{V}-V_t$ at the output which is the point at which there is a gate voltage of $V_{gs}=V_t$ and the transistor is about to turn off. If the transistor turns off, the output voltage will go down again and the transistor will start to turn on. Because the transistor is essentially a variable resistance, it will reach an equilibrium where it is turned slightly on. But the output voltage will be floating somewhere in the middle of the supply meaning it is neither a logic 0 nor a logic 1.

Hopefully that helps.

• Very good and detailed explanation but I disagree with the last paragraph. If the MOSFET is turned upside down, the body diode will always conduct and Vout is nothing but V+ - Vdiode. Oct 2, 2015 at 20:20
• @christoph I'm keeping things simple. You are correct that a body diode would change things for that case. Oct 2, 2015 at 21:01
• @TomCarpenter, even if it weren't for the body diode, the FET would be a symetrical device and it would simply work as a source follower with the source and drain nodes mislabelled. It would not block current as your answer implies. Oct 2, 2015 at 21:18
• @ThePhoton Fair enough, guess my memory is a little fuzzy. I've removed that bit. Oct 2, 2015 at 21:45
• Actually, yeah, of course you're right, it's totally symmetrical. duh. Oct 2, 2015 at 22:05

Here I'll use a very basic model of a MOSFET, where it is either fully on or fully off.

I think you're referring to the following situation:

simulate this circuit – Schematic created using CircuitLab

An NMOS transistor turns on when $V_{GS} > V_T$.

The source is always lower in voltage than the drain, so when it is a high side switch, the output node is the source.

If you can drive the gate of the transistor higher than the power supply voltage (e.g., using a different power supply), then you can set $V_G=V_{DD}+V_T$ and there will not actually be any voltage drop across the transistor.

However, usually the highest voltage you can set on the gate is $V_{DD}$. In that case, the transistor will be turned on only when $V_{DD} - V_S > V_T$ (by substituting the gate voltage into the first equation). Rearranging, we have that the transistor is on when $V_S < V_{DD} - V_T$. There is the drop by the threshold voltage you are referring to.