The image below shows a extremely simplified circuit diagram. I do understand the logic behind that. However, the other image(below) is the one i dont understand. It shows a circuit diagram implementing the NAND gate. I do understant how the NAND gates works. However i dont understand the circuit on the left of the image. The truth table shows the correct output of a NAND gate, however, based on the circuit diagram on the left of the image, if A and B is 0 shouldnt the output for Y be 0 as well. I dont understand the symbol beside the Alphabets as well. I dont know how the current in the circuit diagram is flowing as well. Would anyone care to explain how this works? Thank you.
In VLSI the transistors with the little circle on their gates are the p-channel transistors while the ones without it are the n-channel.
When n-channel transistor gate is at the GND level (and source is also at GND) it's in the cutoff state (OFF). There is no conduction between drain and source. When it's at 3.3V the current flows between drain and source causing the drain to be also at GND (ON).
When p-channel transistor gate is at the VDD (3.3V in your case) (and source is also at VDD) it's in the cutoff state (OFF). There is no conduction between drain and source. When it's at GND the current flows between drain and source causing the drain to be also at VDD (ON).
In the truth table assume that 0 = GND and 1 = VDD (+3.3V).
Now figure out in what state is each of the four transistor for all 4 combinations of the inputs A and B. This will help you understand the Y output levels.
For AB=00 both of the n-channel transistors are OFF and both p-channels transistors are ON causing Y=VDD (1)
For AB=01 or 10 only one the n-channel transistors is OFF and only one of the p-channel transistors is ON which still causes Y=VDD (1)
For AB=11 both the n-channel transistors is ON and both of the p-channel transistors are OFF causing Y=GND (0)
Here is how the circuit works for each of the cases shown in the truth table for a NAND gate:
Note that for either or both inputs = 0 (low), the output is 1 (high, or 3.3v). This is because the top two parallel transistors are inverting, so if the input(s) are low, the corresponding transistor(s) will be on, connecting 3.3v to the output. Meanwhile one or both of the series transistors will be off, so ground is inhibited from being connected to the output. This follows the NAND rule, if either (or both) inputs are 0, the output is 1.
However if both inputs are high (1, or 3.3v), then the two series transistors are both on, connecting the output to ground (low, or 0v). 3.3v is inhibited from being connected to the output since both of the parallel transistors will be off since their inverting inputs are high. This corresponds to the NAND rule, if both inputs are 1, the output is 0.
I think your 'extremely simplified' diagram is what's causing the confusion. That's not a CMOS inverter, it's a pmos inverter. You'll notice that it never drives the signal to ground, which is an issue when we're talking about devices with very small current drain.
The second diagram, of then nand gate, is cmos. That's complimentary metal oxide semiconductor. It has a pmos circuit (that's the transistors with the circle on the gate) that's connected between v and the output, and the logical opposite nmos circuit connected between the output and 0. The point being that the circuit can be driven high or low without the use of energy wasting pull-up resistors.
Basically, the top devices are pmos transistors, they are closed when the input is 0 and open when it's 1 (thus the bubble on the gate), the devices below are the opposite. If we take the case of A=B=0, we see that both of the top devices are closed, and the bottom devices are open, So the output becomes 1