I am starting out with programmable logic, and I am mostly using schematic entry. (Hey, I like to see the schematic instead of VHDL/VERILOG :P)

I have been using a Xilinx CPLD originally that had 128 macrocells, and the design has a data bus and used tri state buffers extensively. Turns out it did not fit into the CPLD, and the next step on digikey was a Xilinx FPGA ($5.80), so I figured all I would have to do was change the device to the FPGA in the ISE. Apparently the Tri state buffers do not exist on an FPGA which means I have to redesign a great deal. Also, one of the main reasons I wanted to use a FPGA was because the FPGA can be programmed using a SPI flash instead of JTAG. (I don't have any JTAG programmers, but I have MCU's to program SPI flash) There is the MachXO2 on digikey for similar price but with 640 macrocells, which I figure should be more than enough, not to mention that it can be programmed using SPI flash, and probably has the Tri state buffers.

So, here is the question. When are CPLD's used instead of FPGA's and vice versa. In what applications does a CPLD not make sense, but a FPGA is better suited for?

  • \$\begingroup\$ If anyone is interested in more background to the question, here is a link to the project I am doing relating to this: dangerousprototypes.com/forum/viewtopic.php?f=56&t=2678 \$\endgroup\$ – hak8or Sep 11 '11 at 15:52
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    \$\begingroup\$ electronics.stackexchange.com/questions/19194/… \$\endgroup\$ – Kellenjb Sep 11 '11 at 16:19
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    \$\begingroup\$ @hak8or Tri-state buffers do exist on FPGA's. Actually, I've never seen one that didn't-- and I've been using Xilinx for 20 years! \$\endgroup\$ – user3624 Sep 11 '11 at 16:45
  • \$\begingroup\$ @David Kessner: Out of curiosity, do you mean tri-state I/O buffers, or the ability to float buses within the chip? Although there are certainly times when one has to use buses within a chip (e.g. within a RAM or ROM array of any significant size) the existence of buses creates the danger of bus conflicts. How would one design an FPGA with usable interal 3-state buses without the possibility of the device being destroyed by errant programming? \$\endgroup\$ – supercat Sep 11 '11 at 17:11
  • \$\begingroup\$ @supercat I was talking about I/O Buffers. Simply put, don't use internal tri-state busses. Ever. Some early Xilinx parts did have internal tri-states, but newer ones do not. For a while the Xilinx compiler would detect the use of internal tri-states and emulate it with logic, but I didn't use that feature and don't know if it still does that. I have a way-cool method for doing internal busses. It involves a C++ program that I wrote that generates VHDL, C++, and assembly code. We should chat about it sometime. \$\endgroup\$ – user3624 Sep 11 '11 at 17:21

Usually it is a system trade-off. How many voltage rails are needed, how many discrete ICs are required, how much power, amount of logic.

CPLDs, usually, are smaller (less programmable resources), usually require a single voltage rail, do not require an external PROM. As mentioned, usually used for glue logic, in place of discrete gates.

FPGAs are, usually, much large (more logic resources). Require multiple voltage rails, consume more power.

Most projects people describe are most appropriate for FPGAs.


CPLDs are mostly used for random logic that used to be implemented using individual TTL and CMOS chips. FPGAs tend to be used for complete systems or complex sub-systems. There will obviously be some overlap, and Altera CPLDs are actually small FPGAs with on-chip configuration memory.

FPGA I/Os can usually be tri-stated.


A typical CPLD will have a small number of circuits to compute logic functions--typically 1-4 per output pin--but each circuit will be able to act upon a large number of inputs. An FPGA will typically have a much larger number of circuits to compute logic functions, but each of them will only be able to act upon a few inputs.

From a hardware efficiency standpoint, it would seem like it would be best to combine the approaches, since it would seem somewhat wasteful to have to use one out of a small number of 36-input logic circuit to implement a two-input NAND gate, but on the flip side it would be wasteful to use nine separate three-input logic elements, and all the routing associated with them, to implement a seventeen-input AND gate. In practice, though, most devices tend strongly toward either the FPGA or CPLD camp; I suspect that is because while a human might have a good sense of how to implement a smaller project using a variety of different resources, it's easier for software to implement a design if a chip has a large number of resources that are exactly equivalent.

Consequently, I would suggest that a major factor in deciding between an FPGA and CPLD will often be the extent to which a device needs to generate a small number of complicated functions, or a larger number of simple ones.


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