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So I'm having an issue of implementing an 8 bit counter from two 4 bit counters. The first 4 bit works when initiated by the clock pulse and so does the second separately with its own clock pulse. How could I use just one clock to send pulses to have the counter count from 00000000 to 11111111 without having to use two clocks to do so? I'm planning to make a 12 bit and 16 bit the same way and since I plan to make devices out of these to use for a bigger project it'd make sense to understand how to make an 8 bit first.

Key information : I3 is the most significant bit, I0 is the least significant. Cout is the probe connected to the d flip flop in each 'circuit'.

Here's a picture of what I got so far.

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While @optronik's answer is one method of doing it, and the one which uses the least amount of hardware, it's not the best approach.

The issue is one of propagation delays. If you use the MSB of counter 1 as a clock for counter 2 what will happen is there will be a delay between the count values.

When the clock signal for counter 1 triggers it to overflow (go from 15 to 0), there will be a small delay between that clock edge and counter 1's output updating. Once the output has updated, counter 2 will be clocked, but again there will be a delay in its output updating. So counter 1 will change its output \$t_p\$ seconds after the clock, but counter 2 won't change until \$2\times t_p\$ seconds after the clock.

This could cause glitches in whatever the counter output is connected too - the problem will become more apparent the more counters you used. This is why we design synchronous counters instead of ripple counters.


There are synchronous solutions to the issue.

  1. If your counters are ICs - i.e. not something you have wired up from logic gates - you can make the second counter synchronous with the first by using the same clock for both counters (not the MSB of counter 1).

    a) if the counter has an enable pin, connect the enable of counter 2 the bitwise AND of all bits of counter 1 (i.e. a 4-input AND gate). Connect the clock signal to the clock pin of the counter 2.

    b) If there is no enable pin, you need a 5-input AND gate. Connect four inputs to counter 1 and the fifth goes to the clock signal. The output of the AND gate goes to the clock pin of counter 2. There will be a small propagation delay added, but it won't add up if you cascade more timers.

    I should note that the (b) approach requires a negative-edge clock signal to work correctly. If you have a positive edge triggered flip-flop, you can still use this approach, but instead of a 5-input AND, you need a 5-input OR. The four inputs connect to the negated outputs of counter 1 (i.e. the \$\bar{Q}\$ outputs) and the fifth goes to the clock.

  2. If you are wiring up the counters yourself, you can either do the same as in (1), or you can wire up the counter to be and 8-bit counter directly. If you look at your circuit, you should notice that there is a great deal of symmetry between each bit of the counter. Basically you add the same sub-circuit for each bit - so an 8-bit timer would just 8 of the sub-circuits chained together. An n-bit timer, is n of the sub-circuits.

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  • \$\begingroup\$ I'll keep this in mind! Trying to implement it without the ripple as I plan to use many of these and that delay would be really significant in building a 16 bit computer! Thank you. \$\endgroup\$ – Ricardo Rigaroni Oct 7 '15 at 23:48
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The MSB from counter 1 should clock counter 2

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  • \$\begingroup\$ I thought it was a lot more complicated than that. Thank you so much it works! \$\endgroup\$ – Ricardo Rigaroni Oct 6 '15 at 1:25

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