# Can there be “too much” capacitance on a buck regulator output?

I've an MPM3610 buck regulator module with an integrated inductor of 0.47 µH and a fixed internal compensation. It employs constant-on-time regulation. The datasheet gives some application circuits with a ceramic input and output capacitors of only 10 µF.

According to common knowledge (which may be misleading..) more capacitance on the output will reduce output voltage ripple. However, I've no idea how the stability will be affected.

Since I've got quite some space left on my PCB I wonder how much extra capacitance I should reasonably add, taking into account the reduction of effective capacitance due to DC bias effects.

• What does the datasheet say? You need to consider things like inrush current and time needed for discharge in case you want to lower the voltage – PlasmaHH Oct 6 '15 at 13:03
• The datasheet does not say anything about the output capacitance except for the well known relation between output ripple and capacitance and that ceramics are referred due to low ESR. – Arne Oct 6 '15 at 13:20
• If you want to suppress the ripple more, you can add more output capacitance BUT don't place it directly in parallel with the 10uF output capacitor. Instead, make an LC filter so first through an inductor or a choke, after this you can add almost as much caps as you like. The extra inductor or choke will prevent the extra caps affecting the regulator's loop. – Bimpelrekkie Oct 6 '15 at 13:54
• @FakeMoustache: that comment is probably worth of transfer to an answer. – Fizz Oct 6 '15 at 15:14
• Actually, you're in luck. They do show the internal compensation network, including component values, on p. 13 [fig .2]; and it's a type III (like the Altera products from the app note). By the way, are you letting this MPM auto-select its modes or are you forcing CCM? – Fizz Oct 6 '15 at 16:26

If you want to suppress the ripple more, you can add more output capacitance BUT don't place it directly in parallel with the 10uF output capacitor. Instead, make an LC filter so first through an inductor or a choke, after this you can add almost as much caps as you like. The extra inductor or choke will prevent the extra caps affecting the regulator's loop.

Like so:

simulate this circuit – Schematic created using CircuitLab

• Can you explain why that helps? – ACD Oct 6 '15 at 15:39
• Sure, L3 and C2 form an LC lowpass filter, this attenuates (supresses) high frequency components caused by the switching of the regulator. You see that the FB (feedback) signal for the regulator is taken from C1 and not C2. So the regulation loop is not affected (it remains the same) as L3 separates C2 from the loop. – Bimpelrekkie Oct 6 '15 at 15:47
• Why would more capacitance on the FB node affect the loop? Make it too slow? – ACD Oct 6 '15 at 15:54
• @ACD: I'm guessing you mean on the output (to gnd). Adding capacitance there directly lowers the loop bandwidth and decreases phase margin. Adding capacitance between output and FB is a way to fix that [by providing external compensation]. See altera.com/content/dam/altera-www/global/en_US/pdfs/literature/… although details probably differ depending on the type of internal compensation network used in the regulator. – Fizz Oct 6 '15 at 16:12
• @ACD The capacitor at the output is part of the feedback network, changing it's value (by putting an extra cap in parallel with it for example) will move (in frequency) the corresponding pole. This could lead to different behaviour of the loop, even instability (oscillations !). It is not so much a problem that the loop would become slower but that it affects the frequency response of the loop. – Bimpelrekkie Oct 6 '15 at 21:24

There is indeed a "too much" of capacity for switch mode voltage regulators. It is better to invest in more expensive ceramic capacitors with low ESR close to your inductor rather than to add a bank of electrolytic caps just to fill the space. For a typical regulator the datasheet should specify this. If the application circuit is using a specific value and that circuit was used to characterize the regulator I would go with that value +/-10%

• I'm considering ceramics only; no space and board height for electrolytics... – Arne Oct 6 '15 at 13:19
• Too much capacity will cause unstable regulation characteristics and a danger of damaging the voltage regulator if supply is removed (current flow from the output to the input side; some manufacturers have added an internal protection some others not). Too much of capacity will also influence the startup behaviour; some regulators will not start up. – optronik Oct 6 '15 at 13:38

Here are some qualitative considerations for stability as a function of output capacitance ($C_o$) with the MPM3610. First, judging from info in Table1 (p16) of the datasheet, it seems that the part is commonly used with up to 44uF of $C_o$, which sounds like 4X what you plan to use.

The MPM3610 has 3 modes of operation:

• AAM, which is a PFM type of mode, used at very light loads. The good news here is that this type of control is not based on classic feedback type control, and is very insensitive to the amount value of $C_o$ used. It should be possible to put large amounts of $C_o$ and still have stable operation. Ironically though, this won't help you reduce ripple, since this is a hysteretic mode, switching at a level, so ripple is constant amplitude, although variable frequency. For an example of this look at the top right photo on p9 of the datasheet (Input/Output Ripple), which shows light load ripple of ~20mV at 100Hz. If you are using this mode all of the time, then you will need to take the FakeMoustache approach to reducing ripple amplitude. Oh, and passive filters at those kinds of frequencies are not usually small.

• DCM mode, followed by CCM mode as output load is increased. Both of these use PWM with peak current mode control (pCMC). This is a more or less standard feedback approach with an inner current loop and an outer voltage loop, and it is possible to destabilize with excessive $C_o$. But, what is excessive?

The dominant pole in a pCMC power modulator ($f_{\text{pmp}}$) is located at about $\frac{1}{2 \pi C_o R_o}$, where $R_o$ is the load resistance. Looking at datasheet p12 Figure 1, it appears that the error amp has a compensation zero ($f_{\text{eaz}}$) at about 7 or 8 kHz. Ideally you would want $f_{\text{pmp}}$ to be greater than $f_{\text{eaz}}$, so the zero would provide phase boost before the modulator pole showed up.

In reality, it is possible to push this further, allowing $f_{\text{pmp}}$ to be some amount less than $f_{\text{eaz}}$, by being willing to loose phase margin. In the ideal case, phase margin can be near 90 degrees. By allowing the power modulator pole to move inside the compensation zero, this would be reduced. It might be possible to have a $f_{\text{pmp}}$ of about 1 or 2 kHz (while $f_{\text{eaz}}$ is 7 or 8kHz) and still have adequate phase margin (something like 45 degrees). Of course, going to far with this results in a system that's conditionally stable or even unstable.