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I was testing a four-layer PCB and got electric shocks several times when trying to touch the edges of the PCB. The four layers are: top/+15V/ground/bottom layer.

PCB edges

It seems that there are several "white spots" on the edges. And is it possible that the +15 layer get exposed and shocked me? If that is the case, it is quite dangerous.

We manufactured big boards that each one combines several small ones. Then we break each big boards to have small boards which are the final product. So I guess the power layer(+15V) may get exposed at the breaking process. My questions are:

  1. Am I correct?

  2. Is it because we combining small boards into big boards in the wrong way, such that the internal layers get exposed easily?

  3. Is it because our prototype factory did not do a good job?

  4. What are the potential risks under this condition? To the product its self and to users?

Every answer below is great. I chose Olin's because his answer contains most details.

Many thanks!

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  • \$\begingroup\$ Were you touching anything else at the same time? \$\endgroup\$ – HandyHowie Oct 7 '15 at 10:46
  • \$\begingroup\$ Hi, thanks for your reply. I cannot remember clearly what I touched. But I do not think I was touching anything else. \$\endgroup\$ – richieqianle Oct 7 '15 at 10:48
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    \$\begingroup\$ you should easily be able to measure continuitity/resistance at those spots, but i doubt that you can get shocked by 15V unless you are licking the pcb... \$\endgroup\$ – PlasmaHH Oct 7 '15 at 10:55
  • \$\begingroup\$ strange, our experiment only uses +-15V. And I got shocked all the time... \$\endgroup\$ – richieqianle Oct 7 '15 at 10:56
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    \$\begingroup\$ Why are you asking this when you should be looking at your artworks or gerber files to determine whether the copper tracks are exposed? \$\endgroup\$ – Andy aka Oct 7 '15 at 11:05
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If there is exposed copper at the edges, then the board was designed improperly.

Almost certainly whatever software you are using to design this board has a parameter that controls how close edges copper is allowed. Verify the setting, and of course make sure the software is actually checking against this rule.

The software may have not known that the board was intended to be broken apart. In that case, it didn't know to apply the rule. Either fix the setup so the software knows, or check this manually. Either way, it's your responsibility to make sure copper stops some distance from all final edges. 25 mils is usually conservative for edges the board house will make. Break-away edges will have more positional slop, and can affect the board a little distance in. For those, you should use a larger keep-away distance.

Routing a ground plane right across a break away edge is definitely a bad idea.

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When designing a board there should be sufficient pull back of all the planes away from the edge of the board. If the boards use breakout tabs extra care is needed around the tabs to make sure that shorts or exposed copper does not occur.

It is possible that when the boards were assembled in to a panel the board edges may have been violated or shrunk back to the copper by accident.

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vini_i has it right, you should always ensure any pours are well away from the edge of the board. I generally allow at the very least 15 mil (0.381mm) between traces/pours and the edge of the PCB, and I prefer at least 25 mil. Otherwise you can get shocks, shorts, or low resistance between planes. Never run a pour all the way to the edge of the PCB.

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