# Read and Identify Memory Diagram I am so confused, and the book's explanation confuses me more, can anyone explain how to get and identify the following questions displayed? the Book talks about a 2^2 * 3 bit memory but I cant seem to grasp it, I've search the internet but I cant seem to find the correct phrase that would yield any useful resources. How do I read the schematic that indicates how the address space and addressability?

I want to say that the Address space is 2^2 because there four boxes in each column and the addressability is a 4 bit because there are four D's, but I feel like that is wrong and also confused on how to attempt part c

• address 2 is 1,0:the third column. – Jasen Oct 11 '15 at 8:53
• can you explain? also are my assumption on part a and b correct? – learnmore Oct 11 '15 at 9:05
• Looks like a 4 bit memory to me, D0 to D3 being the 4 data bits. The two address lines are partially decoded into three columns, the 4th column that could be addressed by both being high is not implemented – Neil_UK Oct 11 '15 at 9:09
• @user44635 so the address space is 4 bits? then what would the addressability be? also in the last column the AND gates has an inverter so it reaches high. – learnmore Oct 11 '15 at 9:14
• address 2 is 1,0 (on the address lines a1=1 a0=0) – Jasen Oct 11 '15 at 9:19

## 1 Answer

The "address space" is the number of distinct locations that can be decoded from the two address lines A and A. Two bits can take on 22 = 4 different values.

It's a nonstandard term, but I would assume that "addressability" would refer to the number of addresses that are actually decoded and do something useful. In this case, the three columns correspond to addresses 0, 1 and 2 (left to right), so the addressability would be 3. The AND gates across the top do the address decoding. You could also refer to this as the depth of the memory.

The width of the memory is the number of data bits (D through D down the right sde), which is 4. The data at location 2 (the right-hand column) is 0001.