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The IC is the PE42542, a SP4T RF Switch, 9 kHz–18 GHz. It comes in a LGA package with 4 separate ground pads, different pin dimensions, different number of pins on each side, and different pin pitches.

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Why is this footprint so asymmetric in pitch and pad dimensions? From this vicor application note, I have observed that the pads are different sizes depending on if they are I/O or power. For the PE42542, I have noticed that the smaller pads (2,7,12,22) are the four RF outputs, while the large ones are GND. I've also noticed that the pins on the IC are grouped with respect to function. However, I would still like to know why Peregrine could not have picked a standard pitch and pad size. It would make building the footprint a lot easier!

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    \$\begingroup\$ RF applications are impedance and interference sensitive. I would suspect the mixed pitch was a compromise to fit in lga package dimensions. This is not the weirdest thing out there in rf-land \$\endgroup\$ – crasic Oct 12 '15 at 4:18
  • \$\begingroup\$ As for why the smaller pads, when you change track width(for whatever reason) at those frequencies, you'll get impedance mismatches, which in turn will generate reflections. I would be willing to bet that they choose the pad size based on the highest frequency involved. As an example, look around for eye diagrams dealing with impedance mismatches for USB3(which is only 2.5Ghz). The problem becomes much harder as you go higher in frequency and power. \$\endgroup\$ – GB - AE7OO Nov 11 at 12:42
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Care has to be taken at 18 ghz. Compromises and shortcuts taken at for example, L-band, are not acceptable at higher frequencies.

The grouping by function reflects the internal construction of the chip and the manufacturers attempt to improve isolation between the switch ports, which is a very important spec item for an RF switch.

The RF ports will be carefully simulated to give the correct impedance, and not require large pads which could cause unwanted capacitance to ground.

Ground pads will be enormous to allow lots of vias to be placed directly underneath the chip to make as short connection as possible to your ground plane.

You are the designer, if you are not interested in correct operation at 18Ghz then you can likely take some shortcuts. Let's call it a calculated risk.

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