Suppose we have an iterative algorithm like:
r(j) := f(r(j-1))
r(0) := value
And that vhdl i implemened a process for such algorithms (assuming a bit of pseudocode...)
process(x) is
variable r := x;
variable k := 0;
begin
while(k < MAX) loop
r := f(r); -- f( ) could be a vhdl function
k := k + 1;
end loop;
y <= r; -- y is the output of the entity that embodies this process
end process;
Would the synthesis result in a cascade of f
logic without pipelining?
Update...
I think i could write something equivalent with a for ... generate
would that make some difference in synthesis terms?