# loop synthesis vhdl

Suppose we have an iterative algorithm like:

r(j) := f(r(j-1))
r(0) := value


And that vhdl i implemened a process for such algorithms (assuming a bit of pseudocode...)

process(x) is
variable r := x;
variable k := 0;
begin
while(k < MAX) loop
r := f(r); -- f( ) could be a vhdl function
k := k + 1;
end loop;
y <= r; -- y is the output of the entity that embodies this process
end process;


Would the synthesis result in a cascade of f logic without pipelining?

Update...

I think i could write something equivalent with a for ... generate would that make some difference in synthesis terms?

• Yes. Update .... and No. (Probably). Some synthesis tools may have trouble synthesising one form, though you will most likely get an equally large and slow result either way.
– user16324
Oct 12, 2015 at 14:00
• How could be designed an iterative algorithm? I mean you said (a priori and of course you're right) that that design is gonna be large and slow. Ok but are there better way for such design (in general)? I suppose the answer depends how the recursion/iteration is formulated. Oct 12, 2015 at 14:07
• One more think... to the purpose of simulation (but i think it is different by simulating a real netlist) would be y updated at every clock cycle? Oct 12, 2015 at 14:28
• No. See your sensitivity list. Y will be updated every time an event happens on X.
– user16324
Oct 12, 2015 at 14:33
• but the stuff inside the loop that one is executed in the same clock cycle? this is because i have variable assignment, what i meant is that y at the end of the process will be assigned to the last value the loop computes, isn't? Oct 12, 2015 at 14:40

Your code cannot be synthesised by the logic synthesizers I know. While loops and for loops are unrolled by the synthesizer and must thus have constant bounds. If you want the result to be combinatorial, use a for loop instead:

process(x)
variable r: <r-type> := x;
begin
for k in 0 to MAX - 1 loop
r := f(r);
end loop;
y <= r; -- y is the output of the entity that embodies this process
end process;


Note that you can indeed do the same with a generate statement, the synthesis result would be exactly the same:

type r_array is array(0 to MAX) of <r-type>;
...
g: for k in 1 to MAX generate
r(k) <= f(r(k - 1));
end generate g;
r(0) <= x;
y    <= r(MAX);


If you want a sequential result, processing one iteration per clock cycle, use something like:

process(clock)
variable r: <r-type>;
variable k: natural range 0 to MAX;
begin
if rising_edge(clock) then
if reset = '1' then
k    := MAX;
done <= '0';
else
if start = '1' then
r    := x;
k    := 0;
done <= '0';
end if;
if k = MAX then
done <= '1';
y    <= r; -- y is the output of the entity that embodies this process
else
r := f(r);
k := k + 1;
end if;
end if;
end if;
end process;

• What's the difference between your first code snippet and the mine? Other than the use of a "for" instead of a "while" i don't see the difference. Oct 15, 2015 at 7:25
• The condition of your while loop is not static, it depends on a variable k. The synthesizer is not smart enough to analyse the body of the loop and discover how many iterations will be needed. In a for loop the index is a locally declared constant that cannot be modified in the loop body. So, if the bounds are constant and there are not next or exit statements in the loop body, the synthesizer can statically know how many iterations are needed. Oct 15, 2015 at 7:41
• Ah ok (i was using pseudocode anyway so i didn't focused much on the all the details on the variable itself), but thank you. Oct 15, 2015 at 8:14