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I wish to make sure the input files are checked into source control so I (or others) can build, recreate, branch/modify a design. However with PlanAhead, the same suffixes are used for both input and output files.

Yes, I did ask Xilinx in a WebCase, but didn't get a good answer. I don't wish an answer on the lines of "all of these directories" where that includes many output files. Some of the suffixes are in this question but that answer isn't sufficient since xml files are used for both inputs and outputs.

Knowing what files/directories aren't needed would also be helpful. Then I could ask Xilinx about those files/directories that aren't known.

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1 Answer 1

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  1. The .ppr file is the PlanAhead project file.
  2. Assuming the project is named project, it references these files which appear to be needed
./project.data/constrs_1/fileset.xml
./project.data/sources_1/fileset.xml
./project.data/runs/runs.xml
./project.data/runs/impl_1.psg

runs.xml seems to also contain output/status information so changes onrecompile.

impl_1.psg contains bitgen options.

  1. Assuming ChipScope
./project.sources_1/chipscope.xml
./project.data/sources_1/cs/u_icon*/u_icon.ngc
./project.data/sources_1/cs/cs_il*/cs_ila*.ngc

Files you don't need:

wt/ (webtalk)

Files that I don't know if needed or not

./project.data/runs/synth_1/constrs_in.xml
./project.data/runs/synth_1/sources.xml
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