# Multiplication Gate Delay

How do you find the gate delay for a basic multiplier circuit that ANDs each bit of the multiplicand with the multiplier then shifts the multiplicand left and the multiplier right until the multiplier is empty, then adds the columns?

I'm trying to figure out the general timing equation for this type of multiplication as well as for the faster carry-save multiplication. If anyone knows of a link that has this information that would be really helpful also.

• The gate delays are usually specified in the chip datasheets. For example, it is in the range of 5 ns for a 7400 series gate. You also need to add in the total time taken for the shifting (how many clock cycles are required to do that?) and the adder - all of those are multiphase operations. You could always make a diagram with all of the components, and manually calculate how long it would take for a signal to propagate through it all. Commented Oct 13, 2015 at 4:44
• Look for tpd or tlh/thl in datasheets. Commented Oct 13, 2015 at 10:07

If you are talking about a general, clocked, shift-and-add multiplier then the total delay will be $NT_p$, where $N$ is the number of bits and $T_p$ is the clock period.The clock period has to be higher than the time it takes for one N-bit addition to take place so in summary Delay = $NT_p \geq NT_N$ where $T_N$ is the time for one N-bit addition to be completed.
For carry save multiplication, Delay = $NT_1 + T_N$, where $T_1$ is the time it takes for one 1-bit addition to be computed.So comparing the two multiplication schemes we can see that carry save addition will be faster than shift-and-add multiplication for $N > 2$.Shift-and-add multiplication is resource efficient whilst carry save multiplication is time efficient.