14
\$\begingroup\$

I'm designing a DC bench power supply and have come to the matter of choosing the output capacitor. I've identified a number of related design criteria, but I'm finding my reasoning still going a bit in circles as I try to sequence these into a sensible design process.

Here's the working schematic to give you an idea what this will go into. The constant current circuit is not pictured.

enter image description here

Here are the considerations/relationships I understand so far:

  • During a fast load step, \$C_{out}\$ moderates the output voltage change undershoot/overshoot) in the interval required for the control loop to respond. In general, a larger capacitor produces a smaller under/overshoot.

  • \$C_{out}\$ participates in the frequency response of the control loop. It contributes a pole by its interaction with the load resistance and a zero by its interaction with its own effective series resistance (ESR).

  • In general, a faster (higher bandwidth) control loop reduces the output capacitance required to achieve a given undershoot.

  • The portion of the under/overshoot produced by the ESR of \$C_{out}\$ (the vertical bit right at the step) cannot be reduced by a faster control loop. It's size is purely a function of the current (step size) and the ESR.

  • The circuit driven by the supply can and often will contribute additional capacitance, for example, the sum of the power rail bypass capacitors in a connected circuit. This capacitance appears in parallel with \$C_{out}\$. It's not inconceivable these may equal or exceed the value of \$C_{out}\$, causing the \$C_{out}\$ pole to move an octave or more downward. The performance of the power supply should degrade gracefully in this situation and not fall into oscillation, for example.

  • The energy stored in the output capacitance lies outside the control of the power supply's current limiting circuitry. While using a large output capacitor may conceal some sins in the control loop design, it exposes the connected circuit to the risk of uncontrolled current surges.

  • When the voltage set-point is turned down, the output capacitor must be discharged quickly enough to meet the specification for down-programming speed, even when no load is attached. A discharge path proportional to the output capacitance and the specified down-programming speed must be present. In some cases the output voltage sampling circuit (resistive divider) may be adequate; in other cases a shunt resistor or other circuit feature may be needed.

So my question is: "How do I approach selecting the output capacitor for my DC bench power supply design?"

My best guess is this:

  • Start with a modest \$C_{out}\$ value, say 100µF in this case.
  • Work backward from the undershoot spec (say 50mV max, 25mv preferred) at the maximum output voltage (30V) for a full load step (0-300mA), and considering the ESR of available capacitors, see what kind of bandwidth I would require to keep the undershoot within spec.
  • Move to a larger \$C_{out}\$ value either to reduce the required crossover frequency or reduce the ESR value.

Am I on the right track? Any guidance from more experienced practitioners will be very gratefully received :)

\$\endgroup\$
  • 1
    \$\begingroup\$ Excellent analysis, I think you have it all in one post. As small a capacitor as you need to tidy up the loop response, but with a loop that will be stable with a larger capcitor (2x, 10x, infinitely) larger? You can achieve loop stability with arbitrarily large output capacitance if you make the dominant pole of the control loop consist of your series pass current source and the output cap. Sounds counter-intuitive, make a stiff supply from a current source rather than voltage source, but it works. See NatSemi design notes and tutorials on some of their later LDOs. \$\endgroup\$ – Neil_UK Oct 13 '15 at 4:43
  • 1
    \$\begingroup\$ Related: I'd be highly tempted to use a MOSFET in place of the 2N3055. | Using NPN / N Channel part for Q1 reduces Vout_max - but you may not care. | Some cctc may not like energy in C_out flowing back into switch if Vin is removed suddenly. \$\endgroup\$ – Russell McMahon Oct 14 '15 at 0:28
  • \$\begingroup\$ Thanks @RussellMcMahon, yes, I've been considering a MOSFET-based design. I think I'll run through that exercise once I've gone as far as I can with this one. I'm planning on installing this circuit as new guts for a vintage HP 721A power supply (design circa 1960) and it already has the mounting for a TO-3 package, so I thought I'd see how far I could get with one of those devices as a first iteration :) Btw, what does 'cctc' mean? I know I'll need to add some shutdown circuitry to turn the pass device off rapidly if the bias power falls before V_unreg during shutdown. Is that what you mean? \$\endgroup\$ – scanny Oct 14 '15 at 4:31
  • 1
    \$\begingroup\$ @scanny -= cctc was a typo :-( -> ccts -> circuits. | If Vunreg falls suddenly - if it may if loaded by other circuits when power is turned off, then Cout may be at say 30V with lots of energy in it. Some circuits can not stand having output cap energy dumped into them in such cases. Some can. The usual simple 'fix' is to add a reverse biased diode from Vout to Vin so Cout discharges back into Vin in such cases. \$\endgroup\$ – Russell McMahon Oct 14 '15 at 6:52
  • \$\begingroup\$ Ah, got it, thanks @RussellMcMahon :) I'll add that to my list of protection circuit features to add after I've got the core bit sussed out :) \$\endgroup\$ – scanny Oct 15 '15 at 18:15
8
\$\begingroup\$

You seem to have the whole circuit in LTspice anyway. A start-up analysis will tell you most things you want to know. Replace your "big" (45 V) DC source with a source that has a pulse definition, i.e. one that starts at 0 V and steps to 45 V within a short time (say 10...100 ns), after a short time (say 1 µs). That way, all the capacitors will be initialized for an unpowered circuit, and you see your regulator doing it's very best to charge the output capacitor. Using this setup, you get the whole picture: First, the uncharged output capacitor produces a dead short across your output, so you see your regulator starting at its max. current. Once the voltage at your output capacitor reaches the desired value, you will also be able to observe any possible overshoot.

An alternative approach would be to include a current source (actually, sink) at the output, stepping between 0 A and your max. desired output current.

As a rule of thumb, I would start with 1000 µF per 1 A of max. designed output current and try (".step param") values below and above (10 µF, 47 µF, 100 µF, 470 µF; 4.7 mF, 10 mF). Also, things won't become too critical: Your pass transistor is an NPN, and this design is basically stable anyway (as opposed to an LDO, which uses a PNP pass transistor). A stability analysis of your circuit might really be a good idea; even though your schematic looks a lot like a linear regulator with a common collector pass transistor at first glance, you really have a common emitter circuit, and those tend to be unstable. The reason is that the output impedance of a common collector amplifier is roughly the transistor's base driving impedance, divided by the transistor's beta and this value does not change in any significant way when the load varies, and it is low. On the other hand, a common emitter ampifier's output impedance is defined by the load itself, which stays within a certain range at best, but can't be designed into the voltage regulator itself, of course. (*)

Here's a source with a really good explanation about a linear regulator's stability, but we have to swap "PNP" and "NPN" in our example, because we are not (!) dealing with the same circuit here. For the "ususal" way the pass transistor is wired in linear regulators, the quote is: "The PNP transistor in an LDO regulator [...] is connected in a configuration called common emitter, which has a higher output impedance than the common collector configuration in the NPN regulator." (National Semiconductor - now TI - app'note AN-1148, section 9)


(*) Had to edit my first version of the answer because I had overlooked some important issues. As can be seen in some comments to other posts, the problem has to do with repairing vintage lab equipment, and you can never learn enough from fixing stuff. Here's an excerpt from Jim Williams' article "The Importance of Fixing", as published in the book ART & SCIENCE OF ANALOG CIRCUIT DESIGN:

enter image description here

Oh how I like the part about fooling yourself...

\$\endgroup\$
  • 1
    \$\begingroup\$ @scanny - note zebonaut's comment about the NPN pass transistor being basically stable!! \$\endgroup\$ – Andy aka Oct 13 '15 at 11:32
  • \$\begingroup\$ Very useful answer, thanks zebonaut :) I really like the start-up simulation you mention, I'm definitely giving that a try. On the NPN stability bit @Andyaka mentioned, we have a gentlemanly disagreement about whether the pass device in this circuit is configured in common emitter or common collector. I say the former, along with Kevin White and gsills. Andy and at least two others believe it's emitter follower. I posted a question on it that's still open if you want to weigh in: electronics.stackexchange.com/questions/192945/… :) \$\endgroup\$ – scanny Oct 14 '15 at 4:13
  • 3
    \$\begingroup\$ I like the quoted piece. \$\endgroup\$ – JRE Oct 15 '15 at 9:06
3
\$\begingroup\$

Basically you need to consider best and worst cases for the load, in terms of its equivalent resistance and its equivalent capacitance (which goes in parallel with your output cap). You cannot design for absolutely any load.

For the extreme values of the load resistor, it's easy enough to decide on some min value as this is determined by the max current your pass element can dish. But you also need to consider a high impedance load because it pulls the output pole to lower frequencies, possibly compromising stability.

If you're going to plug in as load some board that has sizeable bypass/tank capacitors at its input, then you can't ignore their effect on your regulator. Boards with 470-1000uF at their DC input can be encountered without much difficulty.

Also, in practice, your regulator won't react the same to negative and positive transients. You need to evaluate the step response on both positive and negative load dumps. You have to worry whether the SPICE model for the opamp you use is going to be good enough to predict/simulate this difference.

For further reading I recommend Rincon-Mora's book on LDOs. As far as I know, it's the only recent [i.e. in print] book on linear regulators and he has some industry experience (worked at TI). The first chapter of the book has the theory/formulas and some examples for calculating/estimating the transient response and there's a chapter on system design that goes into stability. Alas, as the book focused on board-level regulators, the worked-out design examples in the book (but not the theory) usually assume that the load capacitance is [at least] an order of magnitude lower than the output cap of the regulator. His design approach mantra is basically "the design cycle of a linear regulator usually starts at the output and ends with the input".

\$\endgroup\$
  • \$\begingroup\$ Very helpful, thanks Respawned Fluff :) That book looks great, I found one for $15 (90% off :) on Amazon and ordered it up. I was beginning to think all the linear regulator designers had retired and all their books had gone out of print! :) Regarding the minimum load resistance, I'm thinking step response is worst at top voltage (30V) and current limit steps in at 300mA, so 100Ω would be as low as I have to go. Have I understood you correctly on that bit? \$\endgroup\$ – scanny Oct 13 '15 at 19:11

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Not the answer you're looking for? Browse other questions tagged or ask your own question.