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So in all the phases of the fetch-decode-execute cycle, it says that the "store" phase is used to store any resultant data from the execute phase. What are the CPU steps for that phase? I heard that it was the same steps for the fetch phase but you had to change some things so what are the things you need to change. Here's the fetch CPU activity steps:

1) Address in PC - MAR
2) MAR - Address Bus
3) read signal - control bus
4) Wait for memory
5) content of location in memory
memory - data bus
6) data bus - MDR
7) MDR - IR

The type of processor is an AVR microprocessor 2560 and the layout is Harvard architecture.

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  • \$\begingroup\$ What's the context of your question? And is your question about storing the execute result into a register or writeback to memory? There might be something useful in these slides: pds.twi.tudelft.nl/vakken/in1200/sheets/in1212_7new.pdf \$\endgroup\$
    – PkP
    Oct 13, 2015 at 8:25
  • \$\begingroup\$ What processor? They're not all the same. \$\endgroup\$
    – tcrosley
    Oct 13, 2015 at 8:32
  • \$\begingroup\$ I assume it's Harvard architecture. \$\endgroup\$
    – Josh Susa
    Oct 13, 2015 at 14:46

1 Answer 1

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The "AVR CPU Core" section of Atmel's part datasheets has some information on the AVR microarchitecture. (Page 12 of the ATmega640/1280/1281/2560/2561 datasheet, for instance.)

In brief, though, the steps you've written out here are typical of a von Neumann architecture. The AVR's Harvard architecture uses separate memories and buses for code and data, and pipelines instruction fetch so that there is no need to "wait for memory" to load instructions. (Indeed, the AVR will run most non-memory instructions in a single cycle.)

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  • \$\begingroup\$ Well then would those steps also work for the von Neumann architecture because to be honest I only learned one type of fetch decode cycle so I really have no idea what kind of architecture that was for. \$\endgroup\$
    – Josh Susa
    Oct 15, 2015 at 3:13
  • \$\begingroup\$ It's difficult to generalize. The steps you're describing here are a gross generalization of how some types of CPU work; the real details, particularly in complex modern CPUs, are far more complex. \$\endgroup\$
    – user39382
    Oct 15, 2015 at 3:20
  • \$\begingroup\$ They are starting out simple but I just want to get the basics of how this cycle works before I try anything more complicated. All I want to know now is how the store phase works and how is it different from the fetch phase? \$\endgroup\$
    – Josh Susa
    Oct 15, 2015 at 3:58

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