So in all the phases of the fetch-decode-execute cycle, it says that the "store" phase is used to store any resultant data from the execute phase. What are the CPU steps for that phase? I heard that it was the same steps for the fetch phase but you had to change some things so what are the things you need to change. Here's the fetch CPU activity steps:
1) Address in PC - MAR 2) MAR - Address Bus 3) read signal - control bus 4) Wait for memory 5) content of location in memory memory - data bus 6) data bus - MDR 7) MDR - IR
The type of processor is an AVR microprocessor 2560 and the layout is Harvard architecture.