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How can I generate a inverted signal of a 20MHz Clock signal synchronous to the original signal? (At least, very close to the original)

With a typical HEX INVERTER the propagation delay is already too high (5-10ns).

Should I use a single-ended to differential IC? Couldn't find any references on the internet.

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  • \$\begingroup\$ What is your propagation delay limit? \$\endgroup\$
    – PlasmaHH
    Oct 13, 2015 at 13:12
  • \$\begingroup\$ I don't really have a "propagation delay limit" I just really want the two clock signals in sync. \$\endgroup\$
    – Marco
    Oct 13, 2015 at 13:15
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    \$\begingroup\$ What is this for? \$\endgroup\$
    – pjc50
    Oct 13, 2015 at 13:17
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    \$\begingroup\$ You could apply the skew in the other direction (route the noninverted signal through two inverters), so you get more time between the rising edge and falling edge but less time between falling and rising. \$\endgroup\$
    – pjc50
    Oct 13, 2015 at 13:22
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    \$\begingroup\$ @d3l thats fair. I've only had one issue with the site not being accurate with the datasheet. It's still my goto place to find part numbers or series for me to dive deeper into. \$\endgroup\$
    – efox29
    Oct 13, 2015 at 13:32

1 Answer 1

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You want a buffer with complementary outputs, such as http://www.idt.com/products/clocks-timing/clock-distribution-ics/fanout-buffers-clock-dividers-and-multiplexers/8302i-01-low-skew1-2-lvcmoslvttl-fanout-buffer-w-complementary-output

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  • \$\begingroup\$ Sounds great! I guess the outputs are then more in sync because both signals experience about the same propagation delay? \$\endgroup\$
    – Marco
    Oct 13, 2015 at 13:24
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    \$\begingroup\$ Yes, the device will be designed to give near-identical propagation delay on each path. Note that if you're laying out 74 logic on a PCB you'll have to watch out for skew in the clock wiring. \$\endgroup\$
    – pjc50
    Oct 13, 2015 at 13:29
  • \$\begingroup\$ Perfect, this is exactly what I was looking for. Many thanks \$\endgroup\$
    – Marco
    Oct 13, 2015 at 13:32

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