I am in the process of doing more work on ARM platforms (specifically for this example the Atmel SAMD10 Cortex M0+ line). The clock flexibility and lack of ridiculous fuse settings feels like a (very much overdue) breath of fresh air.
However, I am completely ignorant as to the design compromises at play when considering which crystal frequency to choose and how much to then use the PLL to achieve my target instruction clock.
As an example, let's suppose that my main instruction cycle limitation is that I want to implement a 5Mbps UART using the SAMD10. I want to ensure that instruction cycles are ideally an integer subdivision of the UART bitclock. So I might choose a 20MHz crystal with no PLL multipler - 4 instruction cycles per UART bit and 0 error (theoretically). This all seems fine - 20MHz is a very common crystal value, which should mean good availability and low cost.
But then again 32.768kHz is pretty common - and it seems logical that the crystal oscillator might draw less current at a lower frequency - but I would then need a 1525.9x PLL multiplier to get a 50MHz instruction clock (the fractional PLL outputs only between 48MHz and 96MHz on this MCU). Would this give me worse timing jitter? Is a 1525.9x PLL multiplier big, or well within what you should expect to work for a modern MCU?
How do others choose their crystal / PLL multiplier values in a situation like this?