If your design is not a big commercial thing, I would be tempted to suggest not reinventing the wheel and go with a tried and tested design - especially if you are not sure yet about how the overall design will look
The Papilio Pro board uses the same Spartan 6 FPGA, and its schematic is open source:
(Image from here)
In the past I've successfully replicated the power supply design for a project did at university - and that involved HDMI so was fairly high frequency.
What I can tell you now is that you won't be using all the FPGA resources, it is almost impossible to do that in a realistic design mainly because there are more logic resources than routing resources. Furthermore as you start getting to usage levels higher than 80% you quickly find your design can't run as fast because of competition on routing resources - stuff gets further away so the fmax goes down.
You will also have an incredibly hard time getting a design to run at 350MHz when the global clock tree is only capable of at most 375MHz. The logic will have to be incredibly well pipelined, combinational paths kept to the bare minimum (e.g. no logic functions > 5 input most likely). You'll also have to design it in a way that areas of logic clump together well. Probably even having to physically specify where in the chip stuff goes. For a really complex design I am using an FPGA with an maximum clock frequency of 780MHz, but because of the size of the design and logic complexity, it can barely do the 250MHz I need (271MHz fmax from timing analysis).