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I have a Spartan 6 FPGA (XC6SLX9-2TQG144) and I'm designing a power supply for it.

Let's assume that I will utilize all of its logic (very possible) and I want to clock it as fast as possible (around 350MHz).

How can I estimate the power (number of amps) that my PSU has to supply? Not precisely, but just an order of magnitude. 1.2 V for core and how many amps? 3 A? 5 A?

Side question: is sequencing of power supplies neccessary for this Spartan?

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  • \$\begingroup\$ First off there's no way, unless maybe you made a very specific design that did nothing useful but was only an attempt to max out the part that you will get max speed 100% utilization. Second you should get their power estimation tool, and read the datasheet for power sequencing. I'd be surprised if sequencing is not required. \$\endgroup\$ – Some Hardware Guy Oct 13 '15 at 19:32
  • \$\begingroup\$ As it comes to power, please see my comment below as response to Jotorious's answer. And I ask about sequencing because I've seen recently a project that worked and looked really well but it didn't have any sequencing. \$\endgroup\$ – zupazt3 Oct 13 '15 at 20:04
  • \$\begingroup\$ Good luck... You need a good source and lots of capacitors. Most FPGA families have a whole datasheet or app note to estimate power needs and decoupling needs. \$\endgroup\$ – MadHatter Mar 2 '19 at 18:33
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If your design is not a big commercial thing, I would be tempted to suggest not reinventing the wheel and go with a tried and tested design - especially if you are not sure yet about how the overall design will look

The Papilio Pro board uses the same Spartan 6 FPGA, and its schematic is open source:

Power Supply

(Image from here)

In the past I've successfully replicated the power supply design for a project did at university - and that involved HDMI so was fairly high frequency.


What I can tell you now is that you won't be using all the FPGA resources, it is almost impossible to do that in a realistic design mainly because there are more logic resources than routing resources. Furthermore as you start getting to usage levels higher than 80% you quickly find your design can't run as fast because of competition on routing resources - stuff gets further away so the fmax goes down.

You will also have an incredibly hard time getting a design to run at 350MHz when the global clock tree is only capable of at most 375MHz. The logic will have to be incredibly well pipelined, combinational paths kept to the bare minimum (e.g. no logic functions > 5 input most likely). You'll also have to design it in a way that areas of logic clump together well. Probably even having to physically specify where in the chip stuff goes. For a really complex design I am using an FPGA with an maximum clock frequency of 780MHz, but because of the size of the design and logic complexity, it can barely do the 250MHz I need (271MHz fmax from timing analysis).

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  • \$\begingroup\$ Ok, thanks. I will probably do 3A for I/O with ST1S10. And 5A for core. But I don't know which IC use. All I can find have max. input of 5V and I will have ~8V (from 6VAC transformer...). Do you know what IC will have greater input and 5A? Btw. thaks for the part about MHz etc. I'm begginer in FPGA so probably I won't be able to make it run at max speed and use a lot of resources. In fact I didn't know that it works like that. So I guess that 5A will be sufficient. Do you think that VAUX has to have separate, low-noise supply rail or can it share it with 3.3V I/O? \$\endgroup\$ – zupazt3 Oct 14 '15 at 11:35
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You should download and use Xiinx' power estimation tool. With it you specify the various IOs, logic used, clock speeds, et cetera, and spits out an estimate.

It is here:

http://www.xilinx.com/products/technology/power/xpe.html

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  • \$\begingroup\$ Yes, I know that it's normal order to first make design and then do the power estimate. But because of few reasons (that are here irrelevent) I have to do PSU first. So I will ask different way: what is the biggest number of amps that you have seen in your experience using FPGA of class similar to Spartan6? Or how do you think it could be. Even just roughly. In worst case I will make better PSU than I need... \$\endgroup\$ – zupazt3 Oct 13 '15 at 20:01
  • \$\begingroup\$ @user3144058, the best way to answer that is download the tool and put in estimates of 1.5x or 2x the resources you think your design will use. \$\endgroup\$ – The Photon Oct 13 '15 at 20:34
  • \$\begingroup\$ What is the biggest number of amps I've seen? It sounds like you don't want to figure out an estimate, you want someone to tell you an estimate. \$\endgroup\$ – Jotorious Oct 14 '15 at 20:31
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You should absolutely worry about power sequencing... at least until you read the documentation and it tells you that sequencing is not required. In previous generations sequencing was more of a concern, but according to Xilinx DS162 "Spartan-6 devices do not have a required power-on sequence". Worry about ramp rates (DS162 Table 6), and sequencing in relation to other start-up critical components in your design. For example if your FPGA starts configuration before the voltage rail on the configuration flash comes up, nobody's going to be happy.

You can copy other designs, but ultimately there is no substitute for reading and understanding as much documentation as you can.

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