I'm trying to build a minimal design with PCIe on CycloneIV, and have trouble getting the
core_clk_out to actually run.
In the PCIe user guide, page 13-9, it says that
fixedclk_serdes may not be derived from
refclock for offset cancellation to work.
If I feed this from a free running 125 MHz clock,
core_clk_out does not toggle, however if I connect the
refclock to a PLL block, generate a 125 MHz clock there and connect that to
core_clk_out toggles at 125 MHz.
If I look at a Qsys generated design for the same board, this appears to be indeed correct -- Qsys also generates a 125 MHz clock from the
refclock using a PLL, and uses that for the SERDES.
Can anyone shed some light on this? Is the documentation incorrect, or am I missing something here?