I'm trying to build a minimal design with PCIe on CycloneIV, and have trouble getting the core_clk_out to actually run.

In the PCIe user guide, page 13-9, it says that fixedclk_serdes may not be derived from refclock for offset cancellation to work.

If I feed this from a free running 125 MHz clock, core_clk_out does not toggle, however if I connect the refclock to a PLL block, generate a 125 MHz clock there and connect that to fixedclk_serdes, core_clk_out toggles at 125 MHz.

If I look at a Qsys generated design for the same board, this appears to be indeed correct -- Qsys also generates a 125 MHz clock from the refclock using a PLL, and uses that for the SERDES.

Can anyone shed some light on this? Is the documentation incorrect, or am I missing something here?

  • \$\begingroup\$ Which version is it? Memory Mapped or Streaming (if you post a link to the pdf). The documentation for both is a bit hit and miss (or at least it is for the Stratix V). \$\endgroup\$ Commented Oct 26, 2015 at 23:32
  • \$\begingroup\$ I've used the Megawizard to instantiate the block. I believe the MM/ST differentiation is a layer above that, as the interface to the HIP block is a single 64 bit wide channel that expects the TLP header to be transferred in two cycles, rather than the regular ST interface with dedicated TLP header ports. As I don't even get an application clock, this distinction shouldn't matter though. \$\endgroup\$ Commented Oct 26, 2015 at 23:55
  • \$\begingroup\$ The streaming version has one Avalon-ST sink and one source, it doesn't have anything on top of that, so you have to build the application layer and generate the TLPs directly which I think is what you are going for - I've used the Stratix V version of this in Qsys. There are a few different things that need to be connected up correctly in order to bring the core out of reset. Have you looked at Figure 7-1 on page 166? Does your setup resemble that? \$\endgroup\$ Commented Oct 27, 2015 at 0:39
  • \$\begingroup\$ Yes, for the most part. I've had to connect the input of the PLL generating the reconfig_clk to the PCIe refclock, rather than the free running 100 MHz clock -- hence my confusion, because that is the direct opposite of what the manual says. I can build a minimal example tomorrow morning. \$\endgroup\$ Commented Oct 27, 2015 at 1:04
  • \$\begingroup\$ I would go with what Qsys generates... Have you emailed Altera's tech support with this question? You seem to have specific enough ammo to get this forwarded to a real engineer there. (ie your documentation says not to do this, but Qsys does it) \$\endgroup\$
    – Daniel
    Commented Oct 27, 2015 at 8:20

1 Answer 1


It is hard to say how exactly the offset cancellation circuitry is implemented in the FPGA, therefore the following is my assumptions only.

A usable method, combing auto-zeroing (AZ) and choppering (CH), is described here, p. 39, figs. 2.19 and 2.20. (Yes, it is about op amps in common, but it is very simple to first-time understand, techniques for high-speed serdes may be found as listed here.) As you can see, AZ and CH work on separate, non-equal frequencies (Faz <> Fch).

A PLL outputs a (clock) signal similar but not exact to the reference applied. They may be considered equal in frequency only over a long time averaging (integration), but not in an instant frequency over a self (or comparable) period given, i.e. with a short-term observation they differ. Also, the output of PLL may have a phase shift related to the reference, what make again the signals different in a short-term observation. (For AZ+CH, i think 90-deg phase shift is preferable, if two physically independent clocks/sources are unreachable.)

Therefore, i thing there is no error in the documentation. It is the preferred scenario to clock the offset cancellation, but not the only possible one. (In the doc, it is stated by "cannot" but no "shall/must not".)


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