I've heard that sometimes it is recommended to "slow down" a digital line by putting a resistor on it, let's say a 100 ohm resistor between the output of one chip and the input of another chip (assume standard CMOS logic; assume the signalling rate is pretty slow, say 1-10 MHz). The described benefits include reduced EMI, reduced crosstalk between lines, and reduced ground bounce or supply voltage dips.

What is puzzling about this is that the total amount of power used to switch the input would seem to be quite a bit higher if there is a resistor. The input of the chip that is driven is equivalent to something like a 3-5 pF capacitor (more or less), and charging that through a resistor takes both the energy stored in the input capacitance (5 pF * (3 V)2) and the energy dissipated in the resistor during switching (let's say 10 ns * (3 V)2 / 100 ohm). A back-of-the-envelope calculation shows that the energy dissipated in the resistor is an order of magnitude greater than the energy stored in the input capacitance. How does having to drive a signal much harder reduce noise?

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    \$\begingroup\$ "How does having to drive a signal much harder reduce noise?" You don't drive it "much harder" in order to gain these benefits, e.g. EMI reduction. You drive it the same as before (sans resistor). You size the filter (resistor) according to the desired roll-off. See onsemi.com/pub_link/Collateral/AND8200-D.PDF \$\endgroup\$ Oct 16, 2015 at 10:59
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    \$\begingroup\$ To add on to what Andy and Dimitry explained (which are correct in terms of magnitude and (in a way) frequency of the edge rate (not the bit-rate or switching frequency) this refresher on the Gibbs Phenomenon may be helpful en.wikipedia.org/wiki/Gibbs_phenomenon \$\endgroup\$
    – cowboydan
    Oct 16, 2015 at 16:54

4 Answers 4


Think about a PCB connection (or wire) between an output and an input. It's basically an antenna or radiator. Adding a series resistor will limit the peak current when the output changes state - that causes a reduction in the transient magnetic field generated and therefore will tend to reduce coupling to other parts of the circuit or the outside world.

Unwanted induced emf = \$-N\dfrac{d\Phi}{dt}\$

"N" is one (turn) in the case of simple interference between (say) two PCB tracks.

Flux (\$\Phi\$) is directly proportional to current and so adding a resistor improves things on two counts; firstly, the peak current (and hence the peak flux) is reduced and secondly, the resistor slows down the rate of change of current (and therefore the rate of change of flux) and clearly this has a direct result on the magnitude of any induced emf because emf is proportional to rate of change of flux.

Next, consider the rise time of the voltage on the line when the resistance is increased - rise time will get longer and this means that electric field coupling to other circuits will be reduced. This is due to inter-circuit stray-capacitance (remembering that Q = CV): -

\$\dfrac{dq}{dt} = C\dfrac{dv}{dt} = I\$

If the rate of change of voltage decreases then the effect of current injected into other circuits (via parasitic capacitance) also decreases.

As for the energy argument in your question, given that the output circuit inevitably has some output resistance, if you did the math and calculated the power dissipated in this resistance each time the input capacitance was charged or discharged you would find that this power doesn't change even if the resistor value changed. I know it doesn't sound intuitive but we've been down this argument before and I'll try and find the question and link it because it is interesting.

Try this question - it is one of a few that cover the subject of how energy is lost when charging capacitors up. There is a more recent one that I'll try to find.

Here it is.

  • \$\begingroup\$ Also to gain on my limited understanding (and/or put it into practical terms). Does adding a series resistor "impedance match" the source impedance (e.g. Vdrop/Iout of the source driver) with resistor+characteristic impedance of the PCB traces? E.g. if the source is 100 ohm typ., and your PCB traces are characteristic Z=75 ohm, you would add a 25 ohm (5%) resistor so it reduces reflections. \$\endgroup\$
    – Hans
    Oct 16, 2015 at 16:23
  • \$\begingroup\$ @Hans my answer is addressing the problem of input capacitance and as such it must be assumed that the line length is small compared to the wavelength of the signals involved. In other words this answer is not addressing a different issue namely the characteristic impedance of a transmission line. Also, if the source were 100 ohms then adding 25 ohms makes the source look like 125 ohms and not 75 ohms. Maybe you should raise a new question or maybe I have misinterpreted your comment? \$\endgroup\$
    – Andy aka
    Oct 16, 2015 at 16:42
  • \$\begingroup\$ Thanks, yes I see I confused the resistor by adding it to the line instead of source. But either way, I believe they had to be matched. It was just something on the top of my head which I wondered if it was the same phenomenon. I will probably post it as a dedicated question instead sometime soon. \$\endgroup\$
    – Hans
    Oct 16, 2015 at 17:51

The right term for this "slow down" feature is slew rate. Adding a resistor reduces the slew rate by forming a low-pass RC filter with the input capacitance. You can see the effect of such resistors in the following oscillogram (green curve with higher slew rate produces much more noise):

enter image description here

The power consumption increase you mention is in fact not real. It takes the same amount of energy to charge a capacitor, regardless of how fast you are charging it. The introduction of the resistor only made this energy loss visible, whereas without the resistor the very same energy is dissipated by the CMOS output gates.

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    \$\begingroup\$ Technically slew rate is not the correct term - you may have an amplifier or a driver or buffer with a slew rate limited output but adding a resistor to slow down a fast signal is simply that - it produces an exponential shape and the dV/dt isn't forced to some slew rate limit. \$\endgroup\$
    – Andy aka
    Oct 16, 2015 at 11:34
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    \$\begingroup\$ Exponential shape does limit dV/dt by the initial slope of the exponent, V/(RC). But I do agree with the remark - slow slew rate pins are not made by adding resistors to fast slew rate gates internally. An ideal slow slew rate response is supposed to be linear, not exponential, and independent of the load capacitance. \$\endgroup\$ Oct 16, 2015 at 11:43
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    \$\begingroup\$ Rise time or edge rate, not slew rate \$\endgroup\$
    – endolith
    Oct 17, 2015 at 10:36
  • \$\begingroup\$ @endolith Care to explain the difference between edge rate and slew rate? Rise time is just voltage divided by slew rate, they really express the same thing in different units. \$\endgroup\$ Oct 17, 2015 at 10:46
  • \$\begingroup\$ @DmitryGrigoryev Slewing distorts sine waves, RC filtering does not. Slew rate in op-amps is when the cap is charging from a current source and linearly approaches the final value and then stays there. "Rise time" applies to RC filters charged by a voltage source, producing an exponential decay that (theoretically) never reaches the final value, just asymptotically approaches it. radio-electronics.com/images/op-amp-slew-rate-01.gif radio-electronics.com/images/op-amp-slew-rate-02.gif ee.nmt.edu/~wedeward/EE212L/SP15/RCSquareWaveProbeFig2.gif \$\endgroup\$
    – endolith
    Oct 19, 2015 at 14:18

It's an oversimplification to think of the resistor as 'slowing down' the line, because that's not really what it's there for, at least in high-speed signalling, and it seems to imply that you would reduce or remove the resistor if you wanted to go faster.

In fact, it's series termination for the transmission line which the track represents. As such, its value, plus the output impedance of the driver, should equal the characteristic impedance of the track.

When your driver launches an edge down the line via the resistor, it travels down to the far end at half the final voltage (because there's a potential divider formed by the source impedance and the track impedance), and is then reflected at the open-circuit represented at the far end, which doubles its voltage to the full level. The reflection travels back to the source, at which point it is terminated by the source resistor (via the low impedance of the output drivers).

So the far end gets a nice clean edge, which it can safely use one propagation delay after it was sent (i.e. as soon as possible), and there isn't a set of reflections sloshing backwards and forwards for multiple round trip times, which causes EMI/crosstalk and delays.

The disadvantage is that if you look at the middle of the line, you'll see a funny stepped waveform, which means this isn't always suitable technique for multidrop links. (Certainly not multidrop clocks)


Just to clarify, it's the rise-time of your signal which matters most in these situations, not the frequency with which you generate edges. In an ideal world, you would always have drivers which had edge rates which were sensible for the frequency you were trying to transmit, but that's often not the case nowadays, and if your driver rise time is short, then you need to be thinking about ringing. On a data line, this might not matter (other than EMI), because it will all have stopped before the next clock edge, but on a clock it might be a double-clocking disaster, even if it's a disaster which happens only one million times a second.

Howard Johnson reckons you should be simulating anything longer than 1/6th of the rise-time to see if you need termination. At 1ns rise time that's 150ps, which is about an inch. Other people say things like 2 inches per nanosecond of rise time is the critical length for needing termination.

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    \$\begingroup\$ While reflections in transmission lines do take place, for typical PCB trace lengths (10 cm or so) the reflection would only last for tens of picoseconds, and hardware operating at 1-10 MHz will simply never see such fast glitches. \$\endgroup\$ Oct 16, 2015 at 21:37
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    \$\begingroup\$ What's your derivation of 'tens of picoseconds'? RTT over 10cm of PCB is more like 1ns, surely? \$\endgroup\$
    – user1844
    Oct 17, 2015 at 13:47
  • \$\begingroup\$ OK, twice 10cm divided by the speed of light would be 0.6 ns, so my estimation was way off. Still, 1ns is invisible in systems clocked at 1-10 MHz. \$\endgroup\$ Oct 17, 2015 at 14:36

having to drive a signal much harder

Other way round: the drive strength of a digital output is a fixed quantity(*) based on the size of its output transistors. If you have too much drive strength, you get a large short current pulse. A resistor turns that into a longer, flatter pulse. (I think the area under the pulse on the current-time graph is constant, but I've not done the maths).

The sharper your current pulse, the more you have to consider the system as a transmission line. Then the resistor appears as a source termination resistor.

(*) You can get some devices with switchable drive strength, but that just means they have multiple output transistors per pin.


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