# What kinds of parallel RAM are there?

I have basically no experience in electrical engineering or hardware design, but as an experienced software engineer, I recently took an interest in designing my own CPU. I followed the instructions/excercises presented in the book "The Elements of Computing Systems / Nisan & Schocken", which suggests a RAM design similiar to this:

CHIP RAM8 {
OUT out[16];

PARTS:
}


So there is one "address" bus, which determines which address to read from. Optionally in the same cycle the value of the "in" bus is written to that memory address if the "load" bit is set.

Now I tried to take a spin on the architecture suggested by the book, where I would like to read instructions and data from the RAM in just one cycle (the book proposes a seperate ROM for the instructions). I came up with this RAM design:

CHIP RAM8 {
OUT out1[16], out2[16];

PARTS:
}


So the only difference is basically, that I have introduced a second address bus, so I can read two addresses in parallel at the same time by also introducing a second mux into the chip design.

Now I have several questions concerning this design:

• To me it seems, that the introduction of another mux seems rather cheap to read two items of data from the RAM in only one cycle. Also the hardware design seems totally sound to me (as a total hardware design noob) and simulating the chip seems to proof the design. Am I missing a big mistake/disadvantage of the design? Are there electrical contraints to the design?
• Is this kind of design relevant at all, when reads from a lower hierarchy memory take up several cycles anyway?
• Is this kind of design (reading multiple data items in parallel from RAM) used in any sort of existing, production-ready chips?
• If yes... what kind of chips?
• If no... why?

When googling, the only thing I could come up with was the topic of "PRAM", which refers to "parallel machines", not "parallel memory". Also there seems to be "DDR/QDR RAM" which I don't quite get, since they are still using a single bus to read data (are they reading different items of data on rising/falling clock edges?). But I guess these kinds of RAMs are not really relevant in regards to my design question anyways, since they need multiple cycles to read data anyways, while my design is register based and is able to read randomly accessed memory in only one cycle!?

I would appreciate any kind of information/clarification on this topic :)