I am trying to understand how a basic TIE HIGH and TIE LOW circuit that are based on diode connected MOSFETs followed by a PMOS pullup or NMOS pull down for TIEHI/TIELO accordingly work ?

How does the pull up PMOS transistor turn on in TIE HI ? How does the pull down NMOS transistor turn on in TIE LO ?

I could not find this anywhere in this forum. If not please redirect me to that..Thanks

I have attached the circuit schematic for TIE HI..I understand that diode connected NMOS is always in saturation region and that it can act as diode. But how does the PMOS turn ON ?.

enter image description here

  • 2
    \$\begingroup\$ Where did you get this schematic from? What do you mean by TIE HIGH and TIE LOW? I am unfamiliar with these terms. Using an NFET to drive the gate of PFET is not uncommon, but this is not what is happening in your circuit. Another common use is for a voltage reference in current mirrors. \$\endgroup\$ Commented Oct 18, 2015 at 4:34
  • \$\begingroup\$ TIE HIGH and TIE LOW circuits are meant to pull a node in the circuit to constant HIGH / LOW. Instead of directly connecting a node to VDD/VSS which can have reliability implications (Gate oxide damage), a safer implementation like this is being done.. \$\endgroup\$
    Commented Oct 18, 2015 at 18:11
  • \$\begingroup\$ assigning any node to constants 1'b1/1'b0 in your verilog/VHDL (HDL) translates to one of these circuits that I am talking about. \$\endgroup\$
    Commented Oct 18, 2015 at 18:19
  • \$\begingroup\$ OK, that's what I assumed, but just wanted to clarify. So, is there an input here, or is the diode-connected NFET serving as a constant voltage reference on the gate of the PFET? \$\endgroup\$ Commented Oct 18, 2015 at 23:04
  • \$\begingroup\$ No input to this circuit.. Yes its the diode connected NFET that turns ON the PMOS..That's exactly my question...How is the diode connected NMOS helping to TURN ON PMOS ?. Simulation confirmed that this circuit works fine.. \$\endgroup\$
    Commented Oct 19, 2015 at 2:36

1 Answer 1


I needed to flesh out the details of this circuit before I answered this question!

As you are aware, the N Channel MOSFET is configured as a "diode connected" transistor because the gate and drain are shorted together. Because of this, the MOSFET is in constant saturation mode and acts like a variable resistor.

For an more thorough discussion of this, see this answer here on EE SE.

Now, since a P channel MOSFET is turned on when then gate is held low, and the N channel MOSFET is acting as a pull-down resistor at the gate, the P-MOSFET is also kept in active mode, and allows current to flow from the source voltage through the drain to the output.


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