I've designed a sample and hold circuit (as shown in the snapshot of the circuit attached) but i'm having slew rate problems, if I try to adjust the slew rate (by adjusting the capapacitor and resistor values), the output wave gets noisy and has overshoots. In the circuit, Q1 is used as a switch, Q2 and Q3 have complemetary clock cycles to turn Q1 ON and OFF by adjusting the voltage across Q1's base-emitter. Q4 acts a buffer. I have used NPN transistors BFP280W and PNP transistor BFT93. Ihave attached the schematic, the schematic with annotated dc solution and the output waveforms. I need help to fix the circuit to minimize the errors or maybe suggest a better design if this design seems to be not fixable
The OP seems to have lost interest in this, but I've been thinking about his basic approach, and would propose the following circuit, which takes the idea and makes it fully symmetric. I have not yet simulated it, however.
The key concept is that R1 and R2 are actively driven both high and low by the flip-flop. When R1 is high and R2 is low, Q1 and Q2 are active, driving the capacitor voltage to match the input voltage. In the opposite state, they are quickly cut off in order to isolate the capacitor.