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I've designed a sample and hold circuit (as shown in the snapshot of the circuit attached) but i'm having slew rate problems, if I try to adjust the slew rate (by adjusting the capapacitor and resistor values), the output wave gets noisy and has overshoots. In the circuit, Q1 is used as a switch, Q2 and Q3 have complemetary clock cycles to turn Q1 ON and OFF by adjusting the voltage across Q1's base-emitter. Q4 acts a buffer. I have used NPN transistors BFP280W and PNP transistor BFT93. Ihave attached the schematic, the schematic with annotated dc solution and the output waveforms. I need help to fix the circuit to minimize the errors or maybe suggest a better design if this design seems to be not fixable schematic with annotated dc solution output waveform

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    \$\begingroup\$ Check analog.com/media/en/training-seminars/tutorials/MT-090.pdf from analog deivces \$\endgroup\$ – AKR Oct 19 '15 at 3:56
  • \$\begingroup\$ Q2 would appear to me capable of discharging the storage capacitor - why is this needed? \$\endgroup\$ – Andy aka Oct 19 '15 at 7:50
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    \$\begingroup\$ The circuit appears to be tracking the rising part of your sampled signal, but not the falling side. I suspect you may have turn-off issues in the bipolar devices due to charge injection in the base which requires some time to remove the stored charge. The solution in digital logic was to put a schottky diode across the collector to base junction. See en.wikipedia.org/wiki/Schottky_transistor \$\endgroup\$ – Peter Smith Oct 19 '15 at 8:19
  • \$\begingroup\$ More specifically from my first comment, the capacitor charge path seems ok, but it is not discharging quickly enough (when some discharge is required). if your simulator permits you to look at currents, I suggest doing so to find what in the discharge path is causing the issue. \$\endgroup\$ – Peter Smith Oct 19 '15 at 9:36
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    \$\begingroup\$ Since you say you designed this circuit yourself, maybe you should tell us how you came up with it and why you made the choices you did. How do you think it should work? \$\endgroup\$ – Dave Tweed Oct 19 '15 at 11:58
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The OP seems to have lost interest in this, but I've been thinking about his basic approach, and would propose the following circuit, which takes the idea and makes it fully symmetric. I have not yet simulated it, however.

schematic

simulate this circuit – Schematic created using CircuitLab

The key concept is that R1 and R2 are actively driven both high and low by the flip-flop. When R1 is high and R2 is low, Q1 and Q2 are active, driving the capacitor voltage to match the input voltage. In the opposite state, they are quickly cut off in order to isolate the capacitor.

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