It depends on how far the LVDS driver is from your FPGA and the rise time of the signal (note not the toggle rate)
If the trace is greater than ~1/10 of the electrical length (rise time / propagation delay) then you will probably need to look controlling impedance and termination with a trace of certain width above a ground plane (microstrip) or between planes (stripline)
If less than this (i.e. your LVDS driver is close enough to the FPGA) then you should be fine.
A typical propagation delay for microstrip (a trace above a ground plane) might be 150ps/in. So if your rise time is say, 1500ps then your electrical length is 1500/150 = 10in. So a trace longer than 1 inch will need consideration (some would say 1/6 of the electrical length or 1.6in, see the NI note)
Often just terminating at the source will do, as the reflections will only "bounce" once, and power consumption will be lower than with other techniques. You can do this with a series resistor equal to the difference between the output impedance of the driver and characteristic impedance of your trace. So if your driver has an output impedance of 20 ohms, them your series resistor will be 30 ohms (assuming a 50 ohm trace - note the impedance can change a bit depending on logic state)
IBIS models and simulation help, and SPICE can model a basic transmission line. You may want to play around with a simple setup based on the notes below in SPICE to get a feel for it.
There are many other ways to tackle this, and a lot more to it than outlined above - here are a few decent app notes on termination:
Transmission Line Terminations - UltraCAD
High Speed Layout Guidelines - TI
Proper Termination for High Speed Digital I/O - NI
FR4 propagation delay