I am currently developing a small low power (high switching) Buck converter and have run into a strange issue that I have never seen before and was looking for some insight into the issue. I am also controlling the FETS from an MCU, so I can set up arbitrary dead-times ect.

On the falling edge of the lowside gate, the high side immediately turns on. (As shown below) The first jump in the yellow trace is the HS turning on from the falling edge of the LS signal, while the second jump is the actual HS gate signal. This is regardless of the load I place on Vout.

*EDIT I have revised the image such that it shows the SW node and the Voltage on the gate. The reason I know that it is turning on is that I am getting ~25mA current draw through the main supply signifying a shoot-through occuring. This is again without any load on the IC. There should be ~.6V when the low side turns off since the inductor is causing the diode to forward bias.

Yellow Trace = HS gate, GREEN Trace = LS GATE

I have tried a few different gate drivers that I have available, but they are all acting like this.

I assume that this is a layout issue, but I am not sure exactly what is going on to cause this to happen. I know that it has something to do with the FET input capacitance, but I don't really know how to measure/improve.

Troubleshooting performed:

  • Increased gate resistors to slow down switching
  • Placed pull down resistors on gates (HS to SW node)
  • Tried clamping SW point to HS gate with shotcky diode

As for the layout (this was a prototype board to test out a couple of ideas) I am severally constrained in terms of space to ~1" width on the board and 2 layers (as this is from a local protoboard shop).

Thus the FET driver is located on the opposite side as the FETs, but I have done as much as possible to lower the inductance (multiple VIAs, large traces, ect)


I should also note that there is a throughhole decoupling cap across the GateDrviers VCC/COM that is not shown here. Also there is a LS gate resistor that is not shown in the image.

I am quite puzzled over this, hoping that someone has seen this issue before and can lend some insight.


EDIT 1 To anwser some questions:

1) I have posted another scope print out that shows the SW voltage. The HS is coming on when the LS falls. I can also see this through the current (~25mA @17VDC, also the current draw is directly related to the input voltage...)

2) I am using a MCU to control the PWM, so there is no controller. The MOSFETS are BUK7Y153-100E.

  • 5
    \$\begingroup\$ Post the schematic and the link to the datasheet of the controller IC, please. \$\endgroup\$ Commented Oct 19, 2015 at 19:14
  • 1
    \$\begingroup\$ Looks like the normal operation of a boot-strapped high side driver. \$\endgroup\$
    – Jon
    Commented Oct 19, 2015 at 19:18
  • \$\begingroup\$ Remember that the output inductor will maintain current flow when the lower MOSFET is switched off. If you haven't turned the upper MOSFET on, the body diode will conduct instead. \$\endgroup\$
    – Jon
    Commented Oct 19, 2015 at 19:29
  • \$\begingroup\$ Also, what is the timebase setting on your scope trace? \$\endgroup\$ Commented Oct 19, 2015 at 19:41
  • \$\begingroup\$ I have updated the post. Thanks for the responces so far! \$\endgroup\$
    – spinnerBot
    Commented Oct 20, 2015 at 0:30

2 Answers 2


You're only looking at Vg on the top fet, not Vgs, which is what actually turns it on. Unless you know something which is not on that scope plot, then that first rising edge is not the top FET turning on, it's the source and gate rising up as the bottom FET turns off.

This is what a typical high-side MOSFET driver does in a half-bridge - it floats the drive of the top FET on top of the upper/lower source/drain junction node.


OK, assuming that what I already wrote is not the confusion, here's a mechanism which can cause brief shoot-through on half-bridges with big FETs, though it happens at the top turn-on point, not the bottom turn off:

A MOSFET has an implicit capacitor between gate and source, which everyone knows about and is what you have to charge up to turn on the device. However, it also has capacitance between drain and gate. When the upper FET turns on, and pulls up its source, current flows through this capacitance in the lower FET into the lower FET's gate circuit. Depending on how hard the lower gate driver and lower gate resistance hold the gate down, you might see it turn on briefly/slightly as its drain, and hence gate, is pulled up by the top FET.

This tends to be a much worse problem when the PSU is very lightly loaded.

The problem with just changing both gate resistors is that you don't see much difference, because although slowing-down the turn-on of the top FET helps, increasing the gate resistance on the bottom FET makes the problem worse, and the two effects cancel-out.

To start with, you could just slow-down the top fet by increasing its gate resistor. You may then have to increase your anti-shoot-through delay to avoid problems in at the other end of the cycle, but I'd suggest you make that absurdly big at the moment anyway to eliminate that from your search.

I have ended-up with diodes around gate resistors in this situation, to allow me to set turn-on and turn-off rates separately.

You might find looking closely at both ends of your bottom gate resistor with the scope lets you see this happening. It doesn't sound like you have a current probe available, but for the sake of experiment you could perhaps try adding some low resistance in the 0V line somewhere which would let you see exactly when the shoot-through current spike occurs.

You should post the schematic.

  • \$\begingroup\$ Sorry. I should have mentioned that the SW node was also seeing voltages it should not have and that there was ~25mA (@17V Vin) current draw from the Vin when there was no load applied. This is regardless of duty cycle so I know that I am getting shoot-through. I will post a picture of the SW Point with the input signals. Thanks! \$\endgroup\$
    – spinnerBot
    Commented Oct 20, 2015 at 0:12

This all looks normal for a synchronous buck, where \$I_o\$ is not high enough to keep the inductor current (\$I_L\$) positive throughout the cycle. Let's go through states of the switching cycle:

  • Starting just before the low side gate turns on. \$I_L\$ will be positive, flowing from switches through the inductor to \$C_o\$. Body diode of low side FET conducts \$I_L\$.

  • Low side gate turns on. You can see the step from body diode conduction to FET channel conduction.

  • Low side FET is on. Meanwhile \$I_L\$ is ramping down, and eventually becomes negative, which means current starts to flow from \$C_o\$ back to switches. If you look closely, you can see that while low side switch is on, \$V_{\text{ds}}\$ goes from slightly negative to slightly positive (or at least has a slight positive slope.

  • Low side FET switches off. But, \$I_L\$ is still negative and has to go someplace, so \$I_L\$ flowing back to switches forces \$V_{\text{sw}}\$ up to a body diode drop above \$V_{\text{in}}\$ to allow \$I_L\$ to flow back to the input power supply. Of course the slope of \$I_L\$ changes here from down slope to up slope. \$I_L\$ value is still negative here, but trending toward zero.

  • High side FET switches on. You can see the step where the high side switch goes from body diode conduction to channel conduction. It appears that after about 2uSec of the high side switch being on, \$I_L\$ becomes positive again. You can also see from the slope of \$V_{\text{sw}}\$ while the high side switch is on, that the impedance of \$V_{\text{in}}\$ is too high, or that there isn't enough capacitance to support the load or \$I_L\$ ripple demands.

The amount of time the high side switch body diode conducts can be reduced by increasing \$I_o\$ so that \$I_L\$ spends less time being negative. If \$I_L\$ is never allowed to be negative, the high side body diode would never be conducting. In that case you would see the low side switch body diode conduct for a short time before and after low side turn-on, and no \$V_{\text{sw}}\$ dwell time at \$V_{\text{in}}\$.

Photo doesn't show any indication of cross conduction or shoot through. The 25mA of current from \$V_{\text{in}}\$ is only about 0.4W, and could be easily explained by high ripple current in the inductor. For example if \$\Delta I_{\text{L-pk}}\$ is 2A and there is circuit resistance of about 0.3\$\Omega\$, that would be about 0.4W from \$V_{\text{in}}\$.

It is likely that the inductor value is too low for the circuit loading, meaning that \$\Delta I_L\$ is also too high.


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