I want to create an assignment which takes care of pull-ups from a port pin. I wrote the following:
module test5; reg value; reg output_enable; reg pullup_enable; wire pullup_helper; wire value_helper; wire outp; assign (highz0, pull1 ) pullup_helper = pullup_enable; assign value_helper = output_enable ? value : 1'bz; assign outp = value_helper + pullup_helper; always @(pullup_helper) $display ( "pullup_helper %b", pullup_helper ); always @(value_helper) $display ( "value_helper %b", value_helper ); always @(outp) $display ( "outp %b", outp ); initial begin $display ("Start"); pullup_enable = 0; output_enable = 0; value = 0; #1 $display ("1"); output_enable = 1; #1 $display ("2"); value = 1; #1 $display ("3"); value = 0; #10 $display("End"); end endmodule
I got the output:
Start pullup_helper z value_helper z 1 value_helper 0 2 value_helper 1 3 value_helper 0 End
Q: Why does
outp never change?
EDIT: Because the full answer is related to some comments on the given answers I will summarize the results:
As with support from Greg the answer to the problem is in two steps:
The default installation on Fedora 22 is Icarus 0.9.6. This version is buggy. As Greg tested also version 0.9.7 has the same bug. I installed the latest released version v10 (changed version conventions?)
The second part is simply let drive to assign statements into one wire.
assign (pull1,pull0) bus = pullup_en ? 1'b1 : 1'bz; assign bus = output_en ? value : 1'bz;
With Icarus Verilog V10 it works as expected.