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What is the Frequency and Duty cycle and of the waveform at Z (say if input clock frequency is 1.5Khz)

My Understanding:

Two negative edge triggered MOD 12 counters cascaded and reset when the upper counter is at 0110 and lower counter is at 1001.

I know that the upper counter is fed with a clock of f/12 if the input clock frequency of the lower flop is f Hz.

The lower counter has 9 states while upper counter has 6 states.Usually when we cascade MOD N and MOD M counters total number of states is M x N.

The lower counter is MOD 9 and upper counter is MOD 6 and since i am taking the bit next to MSB of the upper counter as the output The frequency should be :

f/9 *1/6 *2 =f/108 Hz

But, for f= 1.215 KHz, the actual answer is 15 Hz but i get 45 Hz.

My doubts:

  1. Since the upper counter is driven by a different clock, how can is calculate the TOTAL number of STATES of this cascaded asynchronous counter setup?

2.How can i get the duty cycle at the Z output??

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When the bottom counter gets to "8", it'll send a positive edge to the upper counter's clock\ input. That won't do anything, however, because the upper counter is negative-edge triggered. Then, as soon as the bottom counter gets to "9", it'll reset itself and the upper counter, so "Z"s output frequency will be 0Hz and its duty cycle will be 0%.

Update:

Just for fun, I redrew your schematic with the RESETs wired to make a divider, added a power-on RESET to make it start up in a known state, and simulated the circuit. The schematic and the "Z" output plot are shown below, and if you want to simulate the circuit so you can play with it, (LTspice) here are the files you'll need.

Just copy them all into the same folder and left-click on the .asc file.

If you have LTspice installed on your machine, it'll start and automagically bring up the schematic editor with the timer schematic already loaded. If you don't, you can get it, free, here

enter image description here

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  • \$\begingroup\$ Ok i agree, when both are positive edge triggered then lower counter counts up till 8 and during 7 to 8 transition, the upper counter is turned ON but as soon as lower counter reaches 9 ,both are reset. So even when both are positive edge triggered your explanation holds right?? \$\endgroup\$ – Ashik Anuvar Oct 23 '15 at 11:05
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    \$\begingroup\$ @dexter_6174:Yes. If you want the top counter to count up one for every "n" bottom counter clocks, then what you'd do would be to decode n from the bottom counter's Qs and use that as the clock for the upper counter. You'd also need to separate the RESETs and use the decodes to reset their own counters only. You'd then use the top RESET to reset the top counter when you decoded the amount of top counter clocks you wanted to accumulate. \$\endgroup\$ – EM Fields Oct 23 '15 at 11:38

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