Using Verilog how do I synthesize the fastest leading zero count on a 64-bit number?
Initially I went with a CASEX(..), with a lot of 01xxxxx, 001xxxxx lines but I understand this synthesizes a barrel shifter which I'm not sure is quick.
My ask is this, what's the fastest way to get to output... what would the gates look like?
I finally came up with this solution but not sure if it will synthesize to something quicker than the above.
The answer to leading zeros in a 64 bit number is either the number of leading zeros in the first 32 bits (if any is a non-zero) or it's 32 + the number of leading zeros in the lower 32 bits. That gives you the answer to the 6th bit of the answer. You then need to find the number of leading zeros in the 32 bit number, so apply the same rules. I had to do an If/else to deal with all zeros.
// Leading zero count of Sj if (Sj_int[63:0] == 64'b0) tmp_cnt = 64; else begin tmp_cnt = 1'b0; tmp_cnt = (Sj_int[63:31] == 32'b0); val32 = tmp_cnt ? Sj_int[31:0] : Sj_int[63:32]; tmp_cnt = (val32[31:16] == 16'b0); val16 = tmp_cnt ? val32[15:0] : val32[31:16]; tmp_cnt = (val16[15:8] == 8'b0); val8 = tmp_cnt ? val16[7:0] : val16 [15:8]; tmp_cnt = (val8[7:4] == 4'b0); val4 = tmp_cnt ? val8[3:0] : val8[7:4]; tmp_cnt = (val4[3:2] == 2'b0); tmp_cnt = tmp_cnt ? ~val4 : ~val4; end o_Si <= tmp_cnt[6:0]; end