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In a four layer PCB scenario with standard layer stack-up (signal, GND, power, and signal), how do you get power into the power plane?

In my case, there is a voltage regulator sitting on the top layer (SMD) and I need to get power from it into the third layer which is my power plane. Is it enough to put some vias near the output pin of the regulator (or output cap)? It is a mixed digital-analog design. (STM32F4 + some DACs).

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    \$\begingroup\$ Please check this PDF. I suggest every PCB designer should have atleast one glance at this document ti.com/lit/an/szza009/szza009.pdf \$\endgroup\$ – ammar.cma Oct 23 '15 at 17:30
  • \$\begingroup\$ I've seen this document before. But I'm not sure how this is related to the question I've posted. My be I'm missing something. \$\endgroup\$ – Michal Oct 23 '15 at 19:45
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That's the general idea the number of the vias depends in how much current you want to carry and how low of an impedance you are looking for. I suggest you look at the datasheet for your regulator. No doubt there is a recommended layout at the end and if not I'm sure there is an eval board layout you could examine as well.

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  • \$\begingroup\$ Well. I was trying to find any info about this but I was not successful. Do you have any links to datasheets or publicly available eval board PCBs where I could see this? \$\endgroup\$ – Michal Oct 23 '15 at 17:20
  • \$\begingroup\$ Have you looked at the datasheet for the regulator you are using? What is the pn \$\endgroup\$ – Some Hardware Guy Oct 23 '15 at 17:49
  • \$\begingroup\$ Sure I did. Unfortunately I didn't found something useful regarding this. Here is the link: st.com/web/en/resource/technical/document/datasheet/… \$\endgroup\$ – Michal Oct 23 '15 at 19:39
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If you have a voltage regulator on the top layer and want to route it to another layer, then yes, you use vias. Generally you want the vias to be as large as possible. The trace width, via diameter, and via count will depend on the current you expect they will carry. You can use online calculators like this one based on IPC-2221 to determine how wide you need your traces to be. For the vias, I generally try to make the via diameter match the trace width. I also put multiple vias in to ensure good connection and good current carrying capability, because the surface area of the trace could be reduced in the via barrel. A good rule of thumb is one via per half amp. Put these vias as close to the regulator output capacitor as you can.

These are just some basic rules of thumb to get you going.

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As mentioned, use a sea of vias to create a low resistance path between layers. There are online calculators for trace resistance, and these can be used to calculate the resistance of a via based on its diameter, length, and copper thickness. Plus, there probably are specialized calculators specifically for via performance. The design becomes a tradeoff of the number of vias versus the diameters. You can optimize this for the space you have to work with.

http://www.ultracad.com/articles/viacurrents.pdf

http://www.pighixxx.com/test/tools/pcb-via-calculator/

Using this technique, I did a 21 slot VME backplane with 50 A of +5 V per slot on internal layers. First article had less than 15 mV drop between any two points.

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  • \$\begingroup\$ 50 amps per slot and 21 slots. That's a total of 1050 amps in your board. When you say VPX backplane do you mean a giant hunk of solid copper? \$\endgroup\$ – scuba Aug 26 '17 at 3:15
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    \$\begingroup\$ One of the major design features of VPX is lotsa power per slot. This was VME (OK, modified VME), 9U boards, 6kW per chassis. 16 high power slots, plus 5 normal slots. Big fans. \$\endgroup\$ – AnalogKid Aug 26 '17 at 3:51
  • \$\begingroup\$ wow. I get the per chassis thing but all that current has to go through your one backplane board, how big is that backplane?? \$\endgroup\$ – scuba Aug 26 '17 at 11:52
  • \$\begingroup\$ 14 layers. (minimum character count buffer) \$\endgroup\$ – AnalogKid Aug 26 '17 at 12:09

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