Below is circuitry including a 2-input NOR gate, a 2 input OR gate with 2 inputs inverted, and an finally going through an AND gate.
Through experimentation I measured the propogation delay of each logic gate:
AND - 14ns, NOR - 4ns, NOT - 8ns, OR - 12ns,
How do I estimate the total propogation delay of the circuit above? Do I simply add up all the logic gate times? here's my solution:
4ns + 8ns + 12ns + 14ns = 38ns
Is this correct?