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I have to design a BJT multistage amplifier to meet a specification provided by my professor. The first stage is to be a differential amplifier, and the second stage is to be a common collector amplifier. However, the first stage won't be a differential amplifier in the traditional sense; it's to be thought of as a common collector fed into a common base. Overall it's common collector -> common base -> common collector. See the circuit below.

schematic

simulate this circuit – Schematic created using CircuitLab

The capacitor C4 is to short out the 10k resistor at AC, so the left half of the differential amplifier acts like a common base. The power supply does not have to split, I just found it to result in a higher gain that way.

A couple other restrictions imposed on the design by my prof:

-Can only use three transistors; two for the differential stage, and one for the common collector output stage. They can be NPN or PNP.

-Achieve as much gain as possible. Aim for at least 45dB.

-For each transistor, add a 1nF capacitor from the base terminal to the collector terminal. This is to simulate the effects of high frequency while only using a frequency of 10kHz.

-Output stage is to drive a 1k load.

-Add a 10k resistor to the input of the first stage. This represents the output impedance of a previous stage.

Mainly there are two challenges: 1.) Achieving max gain out of the amplifier 2.) Making sure the gain is effective at the frequency of interest.

So essentially the things that can be altered are the Q-point currents and voltages, and the input and output impedances of each stage, which is tricky because they are not entirely independent of each other.

My understanding: Each stage should be designed to have the input impedance as large as possible, and the output impedance as small as possible in order to minimize loading effects. The two common collector stages should be designed to have gain as close to unity as possible. The common base is the "meat" of the amplifier, in that it is the only source of gain.

There must be a maximum value of obtainable gain, and there must be a way to find it. I'm just not sure where to go from here. I came up with a design that can get approximately 35dB of gain, but it was more a matter of messing around with values in SPICE, so I don't have a good explanation of why it works or how to improve it. I have a decent understanding of basic amplifiers, but was never really taught how to design. Any advice is highly appreciated.

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  • \$\begingroup\$ As drawn, there is no DC path to Q3 base. That can't be right... \$\endgroup\$ – Brian Drummond Oct 26 '15 at 0:49
  • \$\begingroup\$ @BrianDrummond, there was a mistake in the circuit that I fixed, but I still don't see what you mean. The positive and negative rails, V_CC and V_EE will supply DC to Q3. \$\endgroup\$ – Lefty Oct 26 '15 at 0:59
  • \$\begingroup\$ @Lefty, before you edited it, R5 and R6 were not connected to the base of Q3. Therefore the base had no DC bias applied to it. \$\endgroup\$ – mkeith Oct 26 '15 at 4:48
  • \$\begingroup\$ @mkeith, I realized that shortly after posting my response. Thanks for pointing that out. \$\endgroup\$ – Lefty Oct 26 '15 at 4:49
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    \$\begingroup\$ Now fixed. One question and hint : are there any constraints on the "frequency of interest" or the required bandwidth, and (given those capacitors) can you think of ways to increase impedance at those frequencies? \$\endgroup\$ – Brian Drummond Oct 26 '15 at 11:15

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