We are learning about general purpose shift registers. My professor draws them with like multiplexers connected to the D's of each flip flop. So in an example of a register with a 4 bit input and output, it looks like 4 Flip flops next to each other connected with each of their D inputs to the output of a multiplexer.

Then i watched this video and it shows a diagram of the register at about 2:08 https://www.youtube.com/watch?v=Fc1FF7dVyaU

Why is that one different? Is the registers with multiplexers wrong? I don't understand my professor very well.

  • \$\begingroup\$ And what are the inputs of the multiplexers connected to. \$\endgroup\$ Oct 27, 2015 at 18:45
  • 2
    \$\begingroup\$ How about an image? \$\endgroup\$
    – jippie
    Oct 27, 2015 at 18:45
  • \$\begingroup\$ Sounds like a shift register that can be parallel loaded. In that case, the regular connections between each register are multiplexed with dedicated data input lines. \$\endgroup\$
    – FRob
    Oct 27, 2015 at 18:51

1 Answer 1


shift registers are divided into serial to parallel and parallel to serial shift registers.

This is serial to parallel:

enter image description here

I think your teacher was teaching parallel to serials. The seria to parallel SR above looks like a demultiplexer in a way that they both have less input and much output. The difference is that in serial to parallel shift registers there is only one data input. In demultiplexers, 2 or more. You see, ifyou apply 2 input pins of a demultiplexer, you can have 2 over 2 output, you can set each output by 2 pins like 00, 01, 10, 11 and then apply the input data to the chosen output(one output at a time). But in serial to parallel SR, you have to aply input pins one by one, and then you can buffer them all in once.

And here is parallel to serial SR:

enter image description here

You will see the MUX between D flip flops. This MUX is 2:1 which means when you apply 0 to SET pin, the data in the pin 0, will be output otherwise data in the pin 1 will be the output. See the timing diagram which I draw perfectly(Not!):

enter image description here

when t=0, S pins of the MUXs will rise and each D's will pulled by their 1st pins(Pd, Pc, Pb, Pa) and while S is high clock of D flip flops will rise on t=1. Then S will be pulled down. So afterward, with each clock rise, Q's of the D flip flops will be passed to D's of next Flip flops. And since S pin of the Mux is pulled down, for further iterations, only given parallel inputs will be passed through the SO output. I hope this was helpful.

edit: I forget to give a reply to the main question. Not all the registers have multiplexers. But parallel to serial SR's have. Multiplexers are just digital blocks and widely used in digital systems. So, multiplexers are not avoided to use in register or in any digital block at all.

  • \$\begingroup\$ thank you! what happens when the number that gets shifted goes to the end? \$\endgroup\$ Nov 1, 2015 at 4:20

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