Assume the following, generic, configuration in which two digital circuits are interconnected but have independent power supplies (e.g. two redundant microcontrollers).


simulate this circuit – Schematic created using CircuitLab

Now, what happens if V1 is ON but V2 is OFF (or vice versa)? I generally protect against this scenario by inserting resistors on the lines such that the short circuit current is below the max sink current of the pins.

  1. Is that necessary (perhaps something to look for in the datasheets?)? What would happen to the transistor level if no protection was included? Generally, enhancement mode MOSFETs are used, which means all switches are OFF (open) when no voltage is present, therefore I do not understand why there could be an issue.
  2. Are there other means of protection? Those resistors prevent me from running communication lines at high frequency because of the time constant with the input capacitance.

This must be a question that has already been addressed but I can't seem to find any on SE.

Note that this question is only about protecting against unlikely or short events - both supplies will be ON for nominal operation.

  • 2
    \$\begingroup\$ It depends entirely on how the circuits are built. Between nothing and escaping magic smoke, everything is possible. \$\endgroup\$
    – PlasmaHH
    Oct 28 '15 at 12:39
  • \$\begingroup\$ Could you expand on what the outcome depends on, if possible give examples? Anything to look for in the datasheet to determine if it is safe to mate as is? \$\endgroup\$ Oct 28 '15 at 12:40
  • \$\begingroup\$ How high is high frequency? \$\endgroup\$
    – Arsenal
    Oct 28 '15 at 13:17
  • 1
    \$\begingroup\$ This can happen. \$\endgroup\$
    – Fizz
    Oct 28 '15 at 13:45
  • 1
    \$\begingroup\$ High frequency is up to ~100MHz, standard digital communications. \$\endgroup\$ Oct 29 '15 at 14:05

What you are looking for in the datasheet is the pin structure schematic (or diagramm).

It may look something like this: STM32F401 pin strcuture

What you see here in particular are the protection diodes which clamp input voltages to the allowed region. Often it is given as Vdd+0.3 V and Vss-0.3 V or something like that.

The 0.3 V is the voltage drop of the protection diodes. If you have a voltage higher than Vdd+0.3 V the protection diode will start to conduct and supply current to the rest of the circuit.

Your circuit and the controller is of course not supposed to work in that way. For example you could be reverse biasing your voltage regulator on the other side, if the power failure is caused by the input of the voltage regulator breaking down (details depend on the way your power circuit is designed). This can damage your voltage regulator.

Depending on the current draw of the other circuit the actual voltage might be quite a bit lower so the components won't work as expected. For example when driving 20 mA the voltage of the output is reduced by 1.3 V:

Pin voltage levels depending on current

So running from 3.3 V you'd get 2.0 V at the output and only 1.7 V as the new VDD on the other side. Which might cause all sort of troubles (some chips work already, others don't).

I'm not sure on the protection side of things, but maybe a power supervisor which holds the MCU in reset until both voltages are OK might work, as you then can be sure that both are powered correctly.

If you need to have one running all the time you might use a supervisor on each side for the other side and turn off all lines between them if the state is not okay, but as the reaction won't be instantaneous (software involved) it might be too slow.

  • \$\begingroup\$ Very good answer, thanks for the step by step. Is powering the OFF circuit from the ON circuit signal lines the only issue, or are there others I am not aware of? \$\endgroup\$ Oct 29 '15 at 14:09
  • \$\begingroup\$ Btw, you might want to rephrase that: "[...] as you might now be reverse biasing your voltage regulator on the other side [...]" \$\endgroup\$ Oct 29 '15 at 14:09
  • \$\begingroup\$ @MisterMystère I'm not aware of other issues right now. In what way should I rephrase it, for me it's clear, so I don't know what's misleading or not understandable about it? \$\endgroup\$
    – Arsenal
    Oct 29 '15 at 14:17
  • \$\begingroup\$ I don't understand, either it is "as you might know" and what is left is a full sentence, or it is "as you might now" and neither what's before nor what's after seems to be a full sentence either. Maybe there are words missing? Or am I missing something? \$\endgroup\$ Oct 29 '15 at 14:40
  • \$\begingroup\$ @MisterMystère I see, well English isn't my native language, so it's quite possible for me to create meaningless sentences. I've tried to rephrase the paragraph in question. Can you check it? \$\endgroup\$
    – Arsenal
    Oct 29 '15 at 14:49

If your logic supports the Ioff feature as implemented by TI and others, you can safely power down one side without doing any damage to the other side, provided the applied voltages are within the limits specified.

From that thread:

The Ioff feature is for isolating the device when Vcc = 0. The 10 mA is the maximum amount of current the device will input/output while Vcc is 0V. (This refers to the specific device being questioned).

The official definition:

Ioff - The maximum leakage current into an input or output terminal of the device, with the specified voltage applied to the terminal and VCC = 0 V.

The Ioff protection circuitry ensures that no excessive current is drawn from or to an input, output, or combined I/O that is biased to a specified voltage while the device is powered down.

This is an incredibly useful feature and I try and make sure I use these types of devices in power sequencers (in particular), where the power state of some circuitry may be unknown for a short amount of time.


  • \$\begingroup\$ Nice, never heard of that before. What's the meaning of HTH (haven't heard that one either...)? \$\endgroup\$
    – Arsenal
    Oct 28 '15 at 14:28
  • \$\begingroup\$ Hope That Helps :) \$\endgroup\$ Oct 28 '15 at 15:35
  • \$\begingroup\$ Thank you, I wasn't aware of that standard. Now that's something I can look for in the datasheet. \$\endgroup\$ Oct 29 '15 at 14:07

This can lead to things like powering devices through I/O pins, which is generally a bad idea. A common and easy way to fix it is to use an opto-isolator, so that it is impossible for current to flow over the optical gap. This also provides level translation and significant amounts of isolation from high voltages etc.

  • \$\begingroup\$ But might be not suitable for the needed transfer speeds or usable because of power constraints or lifetime limitations of the diode. Notable alternative would be an I-Coupler - I haven't mentioned it so far because I was waiting for a response on how high frequency the signal is. \$\endgroup\$
    – Arsenal
    Oct 28 '15 at 21:46
  • \$\begingroup\$ It's tagged microcontroller, so it's probably low speed enough (<250MHz) for opto isolation to be trivial. \$\endgroup\$
    – user
    Oct 29 '15 at 8:23
  • \$\begingroup\$ @MoJo seems like I'm working in the wrong part of the electronics business, can you point me to an opto isolation part with more than 50 MHz bandwidth? Not that I need it now, but it seems like the sources I usually check don't have any of those. \$\endgroup\$
    – Arsenal
    Oct 29 '15 at 14:57

Use a series diode from each power supply to each Vdd, and increase the supply voltage to compensate. This will allow the input protection diodes to power the circuit, without being loaded by the 'off' power supply.


simulate this circuit – Schematic created using CircuitLab

This won't necessarily allow the input-powered circuit to work properly. It's supply voltage will be lower, due to the drop of the protection diode and any output drop on the data line. If all the lines from the powered circuit are low, then there will be no power at all. However, the current delivered by the data line will be limited to that required to run the unpowered logic, rather than everything else connected to the power supply as well.

  • \$\begingroup\$ Thanks. Could you illustrate with a schematic? \$\endgroup\$ Oct 29 '15 at 14:10
  • \$\begingroup\$ @MisterMystère I did, not because it needed it, but because I haven't played with the circuit editor before. \$\endgroup\$
    – Neil_UK
    Oct 29 '15 at 14:24
  • \$\begingroup\$ OK that is what I thought it was about. So the OFF circuit will be powered by the signal lines (well, if at least one of them is high), but this will prevent other circuits to draw more current as well. Not an ideal solution since the signal lines are still providing power, but a solution that could work in some cases. Thanks. \$\endgroup\$ Oct 29 '15 at 14:44

A lot of bad things can happen with the situation you show, many of which have been suggested by others above, but the damage ultimately depends on what kind of circuit you have for CircuitB.

The biggest thing to avoid are:

  • Having the CircuitB draw to much current from the pins of CircuitA, as you pointed out.
  • Accidentally powering CircuitB through the outputs of CircuitA.

There are a couple of solutions to address these issues, and they entirely depend on a series of engineering trade-offs, like all things engineering related.

  • Isolation: Using isolation to separate both circuits will give you best results, but tends to be costly. Isolating GNDs will give you by far the best results, but isn't necessary.
  • Special IC: Use ICs specifically designed for this. For instance, the TXB0108 or the SN74AVC4T245 feature the Ioff functionality mentioned by Peter Smith.
  • Buffer Hack: Place a buffer (74HC244, or something similar) from CircuitA to CircuitB, and have the Output Enable (OE) pin driven from CircuitB. If OE is active low (as most buffers are), you might need to have the pin pulled-up with CircuitA's supply and have CircuitB pull it down to GND. You could also add weak pull-downs on the output of the buffer to prevent your data lines from floating. You'd have to duplicate this circuit in the reverse direction s.t. you can go from CircuitB->CircuitA.

If CircuitA can control CircuitB's powered state, you can cheat and use a load switch to, in effect, tie VDD2 (from CircuitB) to GND, and then make sure your output pins from CircuitA be driven to GND or tri-stated with pull-downs on the pins prior to powering off CircuitB. But I don't think this is your situation.

  • 1
    \$\begingroup\$ Thanks, that's a good summary and adds info to the other answers. I still don't really know which one to accept... \$\endgroup\$ Oct 29 '15 at 23:45
  • \$\begingroup\$ Accept whichever one you feel answers your question the best. Sometimes I find that it takes a couple days/weeks before I can really understand all the answers and make that call. It needs to sink in some. \$\endgroup\$
    – TRISAbits
    Oct 30 '15 at 5:47

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