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I would like to implement a Finite State Machine in VHDL but I've 2 warnings that appears :

 WARNING:Xst:1426 - The value init of the FF/Latch FFd6 hinder the constant cleaning in the block FSM.
   You should achieve better results by setting this init to 0.

WARNING:Xst:1426 - The value init of the FF/Latch FSM_FFd6 hinder the constant cleaning in the block FSM_0-parent.
   You should achieve better results by setting this init to 0.

If I understand, I think that the problem come from the Init of the state :

-- State machine
type state_type is (    idle, 
                            pga_load, sendBitPGA, clockHighPGA,
                            catchADC, setADC
                            );

signal state : state_type := pga_load;  --  First state of the State Machine is PGA_LOAD

But I don't know hot to change the code to avoid that warning...

Can someone help me?

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    \$\begingroup\$ My experience is that this warning doesn't matter. \$\endgroup\$
    – scary_jeff
    Oct 28, 2015 at 14:56
  • \$\begingroup\$ Ok, so it's impossible to remove this warning? \$\endgroup\$
    – Cabs
    Oct 28, 2015 at 14:57
  • \$\begingroup\$ Have you tried to exchange the position of idle and pga_load in the definition? \$\endgroup\$
    – Botnic
    Oct 28, 2015 at 14:58
  • \$\begingroup\$ @Botnic I just try it but unfortunately it doesn't change anything... \$\endgroup\$
    – Cabs
    Oct 28, 2015 at 15:01
  • \$\begingroup\$ In design summary, click "Synthesis Messages". Find the warning, right click it, and select "Filter all instances of this message". \$\endgroup\$
    – scary_jeff
    Oct 28, 2015 at 15:10

1 Answer 1

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This warning is displayed, when the logic for 'state' can be optimized to a constant value from the behavioral description and if this constant value than differs from the specified initial value.

Just take a look at this smaller example which leads to the same warning:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity constant_cleaning is
    Port ( clk : in  STD_LOGIC;
           y : out  STD_LOGIC);
end constant_cleaning;

architecture Behavioral of constant_cleaning is
    type states is (idle, running);
    signal state : states := idle;
begin
    process(clk)
    begin
        if rising_edge(clk) then
            state <= running; -- constant value differing from initial value
        end if;
    end process;

    y <= '1' when state = running else '0'; -- just some output
end Behavioral;

If this is the intended behaviour, then just ignore or filter the warning.

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