I have to Implement a finite state machine (FSM) that controls a block memory. The FSM receives two inputs, indicating ready when the memory is prepared, read / write (r_w) indicating whether you want to perform a read or write and a reset signal. The FSM generates two variables, oe and we that are the "output enable" and "write enable" of the memory block.
So far I made the state transition diagram and the table of output variables depending on the condition but I'm not sure how can I design the circuit with it