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I am currently taking a class on analog electronics and this is one of the problems that came up: enter image description here

  V 1 = 15V V 1 = 15V, Ueb = Ube = 0.6V, Uce(sat) = 0.2V, β =200, 
  VT = 25mV, R2 = 39Ω, R4 = 4.7kΩ, R5 = 470Ω

I am asked to find the values of R1, R3 and R6 such that the quiescent collector currents of Q2 and Q3 are both 8 mA, and the collector of Q2 is at the potential V1/2 when there is no input signal present(what does this tell me? Is it even relevant since I am only doing dc analysis here?) Are there any general steps to follow? I did some similar analysis with two transistors, and what always needed to be done is find expressions for Ve,Vc and Vb for each transistor and by comparing them make an assumption in which mode it is operating. Here however, I came to a contradiction, namely Q2 seems to be in linear mode, and therefore R6=(V1/2-V1-0.7)/8mA <0. I hope I didn't ask a question too broad. I am not asking for a solution, but merely to tell me the recipe for this kind of analysis.

EDIT:Awkwardly enough, I only now noticed that in fact what seemed to me as a node between the collector of Q1 and the base of q3 isn't one. One can tell just by observing carefully.

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    \$\begingroup\$ Correct, you're calculating a solution for the biasing point (DC analysis) which is the situation when there is no (AC) input signal. So you can ignore all the capacitors. Assuming all transistors are in linear mode is a good initial assumption. If a transistor must be in saturation, it will become clear later. Ic(Q3) = 8mA, how can that current flow to ground ? In the schematic write everything you know (currents, voltages). Make an assumption here ans there and see if that can provide a solution. Some components could have a range of values, for example R6. \$\endgroup\$ – Bimpelrekkie Oct 29 '15 at 12:59
  • \$\begingroup\$ If you could provide an answer, that would be great. I really need to gain a better understanding, to be able to learn about amplifiers. \$\endgroup\$ – Emir Šemšić Oct 31 '15 at 13:34
  • \$\begingroup\$ Giving you just the answer (assuming I have one) doesn't help you much, it's the method I use to get to a solution what matters because that you can apply to almost any circuit. Have you drawn the schematic on a piece of paper and filled in everything that you know already ? Like base of Q2, what is the voltage there ? It's 15 V (V1) - 0.6V (Ube) = 14.4 V. Ic of Q3 = 8mA, where can it flow ? Q3 emitter - R4 - it cannot flow into R5, C3 blocks it, so must go into Q1 base-emitter - R2 to ground. Now do the same for Q2, Ic is also 8mA, it flows R6 -R3 -R2 This adds to the 8mA through R2... \$\endgroup\$ – Bimpelrekkie Oct 31 '15 at 21:50
  • \$\begingroup\$ @FakeMoustache That is the problem. It can then only flow from the node at C4 to the collector, having in mind that the voltage of the collector is 7.5 V, and that the voltage of node at c4 is 14.4 V. Then the collector current is flowing IN to the transistor, which is quite odd here, having in mind that it really seems like this transistor is in linear mode. Btw, I wasn't asking for the solution, but for the method, to hear your way of thinking. \$\endgroup\$ – Emir Šemšić Oct 31 '15 at 21:55
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    \$\begingroup\$ I agree with @FakeMoustache, the question as stated does not work. Q3 collector current must pass through r4 which is not possible with 8ma and 4k7 and 15v \$\endgroup\$ – Loganf Nov 3 '15 at 0:22
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Both the question and configuration seems to be ..broken, somehow, but making a few assumptions/changes, i'll try to illustrate how i would go about solving a similar task. I'm guessing that my assumed configuration is not the intended one, but i can't see any obvious alternative.

So: Assuming all transistors are NPN (and changing parameters for the transistor we have changed to apply to the emitter), assuming collector current targets are Q1 and Q2. (rather than Q2/Q3)

Generally, the approach is to assume a reasonable set of starting conditions and your target state, and then change values until either the conditions are fulfilled or you reach an absurd state (prompting a change in the initial assumptions).

We'll start by assuming linear operation for all transistors (all seem to be implementing basic amplifier configurations, and are if such probably intended to operate linearily.)

Q1 seen from R2 and Q3 seen from R4 are both emitter followers, and since we are assuming linear operation I_R4 should be 8mA/β. the voltage drop over R4 is then (8m/200*4k7 V) small (< 200mV). The voltage drop over R3, going through the two emitters and R4 then becomes 2Ube + ~200mV or ~1.4V.

We now know the voltage over R3. Again, since we are assuming Q3 as linear, the base current into Q3 << IR3, and IR3 must then be close to the collector current of Q2, i.e. 8mA. given our assumptions being correct, we can now set R3.

The current through R2 is then current through R3 + the emitter current from Q1, ~16mA. We now know or assume the voltages across Q2 (U1/2),R3(~1.4V),R2. The remainder of voltage needs to be over R6. The current is equal to IQ2.

If Q2 is to operate in the linear region, the voltage over R1 needs to be ~Ueb over the target emitter voltage. It also needs to absorb most of the current from Q1. I=~8mA, U=U1/2-Ueb

You now have an answer, and all that remains is to see that this really is a steady, non-absurd state. From the operation of the double voltage followers, you can see that that there is a negative feedback loop through the three transistors. If the current through Q2 is too high, the voltage across R3 must also be high, pulling up Q3->Q1 -> pulling down R1-> lowering the voltage on the Q2 base.

Exact numbers left as an exercise for the reader. Beware of horrible coffee-deficiency-induced mistakes in math and logic.

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  • \$\begingroup\$ Check my latest edit. \$\endgroup\$ – Emir Šemšić Nov 5 '15 at 8:08
  • \$\begingroup\$ I never saw a node there. My issue with the circuit is that Q3 seems to be inserted as a feedback amplifier, but if you follow the loop gain around Q1-Q2-Q3 it turns out to be positive (unless i am reading the circuit wrong). \$\endgroup\$ – Brog Nov 5 '15 at 8:39
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Are you sure that you provided all information on this circuit?

As far as I can see, this device only produces some leakage current.

There is no chance for a current flow.

Either Q3 will do something, nor Q1. The only possible current might flow in Q2 form the Emitter to the base but there's still no way to continue.

Even a timing analysis might not change anything because there's no capacitor, that might provide the required base current for any transistor.

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