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I want to make a counter like gray code but this is different , so write this code but help me to find an error

This is the code

module counter2(mainclk,rst , A,B,C,D );
input mainclk;
input rst;
output A,B,C,D;
reg A,B,C,D;
reg [3:0]qb;

reg anb,dnb,bc,nca,nd,na,nb,cna;
reg ap,bp,cp;
initial
begin
A=1'b0;
B=1'b1;
C=1'b0;
D=1'b1;

qb[3]=1'b1;
qb[2]=1'b0;
qb[1]=1'b1;
qb[0]=1'b0;

end
always @(posedge mainclk )
begin
    if(rst)
        begin
            A<=1'b0;
            B<=1'b1;
            C<=1'b0;
            D<=1'b1;
        end
    else
        begin
            anb <= A && qb[2];
            dnb <= D && qb[2];
            ap <=  anb || dnb;
            d_ff dffa(ap , 0 , mainclk , A ,qb[3]);
            bc <= B && C ;
            nca <= A && qb[1];
            bp <= bc || nca;
            @d_ff dffb(bp , 0 , mainclk , B ,qb[2]);
            cp <= qb[0] || qb[3] || qb[2] ;
            @d_ff dffc(cp , 0 , mainclk , C ,qb[1]);
            cna <= C && qb[3];
            @d_ff dffd(cna , 0 , mainclk , D ,qb[0]);
        end
end

endmodule

and the error is Error (10170): Verilog HDL syntax error at counter2.v(37) near text "dffa"; expecting "<=", or "="

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  • \$\begingroup\$ Where is line 37? It's no fun to manually count source lines! Your code has no comments, just cryptic signal names. \$\endgroup\$
    – Paebbels
    Commented Oct 30, 2015 at 6:57

1 Answer 1

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Erm, your d_ff module is a self contained unit, it will contain an always block. You instantiate the module separately (i.e. not in an always block), and use wire for all the outputs and reg or wire for all the inputs.

Once you connect up mainclk to the clock input of your d_ff module and also rst, then it will behave as a flip flop synchronous to all those in your always block.


You don't have to stick everything in the same always block, you can have as many as you need. Any that have the same edge sensitivity list will be synchronous to each other regardless of whether or not they are in the same block.

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