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Let's say I've got an power output and I want to power a chips Vin's with it. But, let's say it's a couple of different digital Vcc's on the chip that I want to power, like a rail for an LO, a rail for a radio, a rail for something else digital...whatever.

So, if the final output of the power supply stage before it gets to the chip is an inductor (like, for instance, L1), and my plan is to keep the power into the chip as noise free as possible so they don't interfere with each other, does this make sense to do? enter image description here

I would think this is pointless and does little to help noise/interference separation. I would think you should do it like this: enter image description here

Am I correct and is there any advantage or disadvantage to one over the other?

Thanks.

EDIT: Please excuse my mockup layout...There is, as there should be, a bypass capacitor on the output of the inductor to ground...My question is more about the tracks coming off the pads. I should have the correct capacitor artwork as well...I assure you, it's there in the real design.

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My answer first makes the following assumptions:

  1. The inductor is really just a place holder for the output of a dc-dc converter (I would assume a buck converter though it doesn't matter what topology).

  2. You're real question is how to properly decouple each of the 3 different power inputs and they power different aspects of the chip (digital and analog etc.) when the power supply is about that far or further away. You're asking about the trace layout mostly because you believe this is, in this case, important.

  3. You have your reasons for the distance between the power supply output and the chip. Perhaps you are hoping to avoid doing that for fear of picking up noise from radiated EMI, which any switching converter will produce to some degree. And proximity is definitely your enemy when it comes to that. Regardless, I'm assuming that you asked about what to do in the situation you asked about to decouple noise, and not how to decouple something in a completely different situation like the other answers to your question.

First off, using one or 3 traces is not important in this case. You do want to minimize inductance when possible, and that is done neither by using a single common trace or 3 separate traces coming from the power output. If you have room for 3 traces, you have room for a single trace that is 3 times as wide. A single wider trace will always have lower inductance than many isolated traces. At least assuming the ground return currents are free to move in a larger plane underneath.

Once you have used this larger wide trace to reach the proximity of your chip, you must, and this is an absolute must, use local decoupling capacitors. They will be the source of power, while the larger loop will serve to recharge those capacitors, but the chip doesn't care and can't tell the difference between a distant power supply and local capacitor or the output capactor on the same supply directly adjacent. Electrons are electrons. The decoupling capacitors, well, decouple the things near by from the larger circuit by acting is local power sources. At least, in a perfect world.

But, heed the warnings about resonance and ringing. Ceramic capacitors have single digit milliohms of impedance. On inrush, they can cause large current transients and form an LC tank with just the few hundred nanohenries inductance from longer trace lengths. This is why you don't just use a ceramic capacitor.

This very real phenomenon can indeed fry or pop all sorts of semiconductors and other sensitive components, but only in improperly decoupled circuits. It's not an actual problem, as it has a very trivial and effective solution: just damp it.

There is no problem as long as you decouple your circuit properly, and properly means critically damping those LC loops.

You can do this with a series resistor (not ideal but cheap and small) or a high ESR capacitor in parallel and proximate to the ceramic decoupling capacitors. Anything above 0.5 ohms resistance (in series or the ESR to ground of a capacitor) will prevent any voltage overshoot from occurring even for meter long traces. Tantalums (non polymer) are great for this, they typically have 1 or two ohms resistance and are small.

So, use a single wide trace, fan it out at the chip with a separate ceramic decoupling capacitor for each supply rail, all connected to the same positiv terminal of a high ESR electrolytic (aluminum or tantalum) and you'll be fine.

http://cds.linear.com/docs/en/application-note/an88f.pdf goes into this with more depth for anyone interested.

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In general, adding an inductor in series with a chip's power feed and not adding decoupling capacitors to ground (at the pins) is really bad. Just don't do this whether you split it into three or just have a common track.

Even if you add capacitance you have to ensure that any changes in the current taken by the chip do not suddenly produce resonance overshoots that exceed the chip's maximum power rails. I've actually done this recently.

The inductor was upstream towards the power supply and I had a 10uF ceramic at the chip to ground. I was testing the board for short circuit survival on the output of the chip (a switching regulator). It didn't survive because when the short on the output was released, the current into the device dropped very quickly and created a big under damped sinewave superimposed on the power rail to the device. It didn't burn or fry but it never worked again.

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    \$\begingroup\$ Indeed, if for no other reason than \$V=L\frac{di}{dt}\$. If the microcontroller suddenly changes the amount current it draws, bang. At the very least you get voltage spikes at every change in current. \$\endgroup\$ – Tom Carpenter Oct 30 '15 at 15:59
  • \$\begingroup\$ @TomCarpenter - thanks for reminding me about a recent design I was doing!!! \$\endgroup\$ – Andy aka Oct 30 '15 at 16:05
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As Andy has answered, putting an inductor inseries with you power rail is asking for trouble.

But as I read it, that is not what your question is about.

Let's assume that the voltage at pin 1 of the inductor is constant, and one of the chips pins draws a varying amount of power (for instance to drive the GPIO output stages), and the other pins draw very little current.

In the first layout the voltage at the other pins will be the voltage at pin1 of the inductor (which we assumed is constant).

In the second layout, the other pins will see the voltage drop caused by the shared trace. In other words: the supply current drawn by one pin will be coupled into the voltage seen at the other pins.

If one of the other pins is for instance an analog reference, the first layout might do significantly better. It is the positive-rail equivalent of the 'single earth point' principle.

But that still leaves the question as to why there is an inductor, and why the trances of those (seemingly important) supply lines can't be shortened by bringing the (decoupled!!) common point closer.

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  • \$\begingroup\$ RE: "Let's assume that the voltage at pin 1 of the inductor is constant, and one of the chips pins draws a varying amount of power"; for OP's benefit, this is a very bad assumption if you don't do something else (like add substantial bypass capacitance) to keep the voltage constant. \$\endgroup\$ – The Photon Oct 30 '15 at 16:17
  • \$\begingroup\$ @The Photon : of course! But as I read it, the OP is asking about the difference between the two PCB layouts, not about the folly of having the inductor. \$\endgroup\$ – Wouter van Ooijen Oct 30 '15 at 16:33
  • \$\begingroup\$ That's my interpretation as well, but having one pin sag and the others not might lead to the device being in a state not allowed (one supply higher than the other), so the second might be safer. But considering the tracks resistance the sag will probably be in a region where it won't affect the operation of the device. \$\endgroup\$ – Arsenal Oct 30 '15 at 17:03
  • \$\begingroup\$ I was thinking of small voltage drops, which could nevertherless affect for instance an A/D converter. \$\endgroup\$ – Wouter van Ooijen Oct 30 '15 at 17:19

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