It's helpful when asking VHDL to question to provide a minimal, complete, and verifiable example pointing to an error.
Here's a solution:
entity some_entity is
generic (n: natural := 9);
x: in std_logic_vector (n-1 downto 0)
architecture foo of some_entity is
entity some_entity_tb is
architecture foo of some_entity_tb is
constant n: natural := 9;
signal signal_id: std_logic_vector (n - 2 downto 0);
generic map (n)
port map (
x(n-2 downto 0) => signal_id,
x(n-1) => '0'
The entire bit analyzes and some_entity_tb elaborates and runs (without actually doing anything useful other than proving connectivity).
You have the ability in VHDL (incl. -93) to associate elements (members) of an array port formal separately.
IEEE Std 1076-1993 188.8.131.52 Association lists, para 14:
A formal may be either an explicitly declared interface object or member (see Section 3) of such an interface object. In the former case,such a formal is said to be associated in whole. In the latter cases,named association must be used to associate the formal and actual; the subelements of such a formal are said to be associated individually. Furthermore, every scalar subelement of the explicitly declared interface object must be associated exactly once with an actual (or subelement thereof)in the same association list, and all such associations must appear in a contiguous sequence within that association list. Each association element that associates a slice or subelement (or slice thereof) of an interface object must identify the formal with a locally static name.
And to explain where the error message:
ncvhdl_p: *E,ILSGRD (test.vhd,159|32): illegal reference of a signal (SIGNAL_ID) during static elaboration [12.3].
IEEE Std 1076-1993, 12.3 Elaboration of a declarative part, para 3:
In certain cases, the elaboration of a declarative item involves the evaluation of expressions that appear within the declarative item. The value of any object denoted by a primary in such an expression must be defined at the time the primary is read (see 4.3.2 ). In addition, if a primary in such an expression is a function call, then the value of any object denoted by or appearing as a part of an actual designator in the function call must be defined at the time the expression is evaluated.
It's telling you that you can't assign an expression as an actual to a formal unless the value of the object
signal_id is known at elaboration time, and a signal's value isn't known until after elaboration:
NOTE--It is a consequence of this rule that the name of a signal declared within a block cannot be referenced in expressions appearing in declarative items within that block, an inner block, or process statement; nor can it be passed as a parameter to a function called during the elaboration of the block. These restrictions exist because the value of a signal is not defined until after the design hierarchy is elaborated. However, a signal parameter name maybe used within expressions in declarative items within a subprogram declarative part, provided that the subprogram is only called after simulation begins,because the value of every signal will be defined by that time.