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For this RTL circuit (RTL inverter with active pull-up):

The textbook says that in the output high state, Qp is in saturation and the circuit looks like:

I wonder how this is possible? $$Rcp = Rc/10$$ and usually $$R_B > R_C$$ so we expect that the voltage at the base is less than the voltage at the collector. And for saturation, we need $$V_{BC} = 0.6V$$

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  • \$\begingroup\$ I agree - it seems misleading what your text book says. At best you could say Vb and Vc are the same voltage so it's borderline. \$\endgroup\$ – Andy aka Oct 30 '15 at 17:50
  • \$\begingroup\$ Does that mean that all of the textbook (Digital Integrated Circuits, DeMassa and Ciccone) analysis that builds on that to calculate the maximum fan-out of the circuit is wrong? \$\endgroup\$ – ammar Oct 30 '15 at 18:14
  • \$\begingroup\$ Never read it so I can't possibly comment. \$\endgroup\$ – Andy aka Oct 30 '15 at 18:18
  • \$\begingroup\$ Take a guess of the gain of Qp. For example, use 100 just to see what happens. Now estimate/calculate Ic vs Ib when Vout is loaded (per the maximum fan-out for example), then Vc vs Vb. \$\endgroup\$ – rioraxe Oct 31 '15 at 1:37
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In the first schematic, only Qs is the (RTL) inverter, Qp and Qo are a classic (in the analog world) totem-pole and in fact the output stage looks a lot more like that of TTL.

If we consider what would be typical values [for TTL] for Rc+Rbp = 1.6K and Rcp = 130 ohm, then a high-quality (high-beta) transistor Qp will be saturated when the output is high. To see this, assume Vcc=5V and Vout = 4V. Then Ic of Qp will be at most 7.7mA (ignoring its Vce). And its Ib would be 0.3V/1.6k = 18.75uA. The resulting minimum beta for saturation is 41. So a transistor with beta of 100 will be [lightly] saturated (which is more often called soft saturation). This is what you want for high-speed switching. If the transistor is heavily (aka deeply) saturated it takes a long time to come out of it, so that's unsuitable for high-speed logic (but it's okay and actually desirable in other contexts like power BJTs, where you want to minimize Vce[sat] instead). By the way, the BJT soft saturation region is also called quasi-saturation. Here it is depicted in a textbook:

enter image description here

As you probably figured out, you can get any behavior from that circuit ranging from active mode to deep saturation, depending on the resistor values. If we decrease Rcp, it will go in the active region, if we increase it, it will become more [deeply] saturated. However, the calculations you have done here seem to ignore the fact that Vo needs to be high. Here's a simulation, with a 2N3904, which has a standard/model beta of 300, and in which we vary the collector resistor from 1 ohm to 201 ohms:

enter image description here

And here is what happens if we additionally vary the beta of the transistor from 25 to 300: a higher beta transistor saturates with a lower Rc.

enter image description here

Finally, I have no idea what resistor assumptions are reasonable for the flavor of RTL that your textbook teaches. This totem-pole speedup (for RTL) is not something mentioned in Wikipedia's page on RTL, by the way. If you're curious about real RTL circuits, read for example the IBM manual linked on that page. (I personally am not interested enough in this topic to do that.)

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  • \$\begingroup\$ By the way, that graphic is a bit exaggerated for a signal transistor (although some power BJTs look like that). For a more realistic depiction of quasi-saturation you could look at books.google.com/books?id=pYJHAAAAQBAJ&pg=PA109 for a common 2N3904. I didn't add that graph because it's complicated with many more things and the region is not terribly well outlined. \$\endgroup\$ – Fizz Oct 31 '15 at 20:06

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