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I would like to have a control signal that stays low all the time and goes hi only when I tell it to. Initializing the pin in the entity does not seem to set the value to zero (xc6slx25-3ftg256):

Entity myEntity IS
PORT(
     -- clock and other IOs
     mySignal : OUT STD_LOGIC := '0'
);
END myEntity;

ARCHITECTURE structural OF myModule IS
BEGIN
-- ...
-- at some point I set mySignal to 'HI'
mySignal <= '1';
-- ...
END structural;

.UCF content

-- other nets
NET "mySignal" LOC = "H15";

I realize that during the configuration, the FPGA structure is not set, so it may have some random values on its outputs. However, after pulling down the pin with 10k, it still stays 'HI' during reset and configuration. How to make it stay low?

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  • \$\begingroup\$ Only memory elements like registets or BlockRAMs can be initialized. A bare pin has no memory. But on most devices it's possible to initialize the pin's output and/or tristate register. \$\endgroup\$ – Paebbels Oct 30 '15 at 22:20
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This sort of thing is device-specific. You need to look at the documentation for your device and see what the behaviour of I/O pins is before configuration. It's most unlikely to be 'some random value' - it's much more likely to be some defined pull-up/down.

As I'm sure you appreciate, nothing you put in your configuration is going to influence the device before the configuration has been loaded...

Update:

Now you've provided some info about the specific device, I'll point you to page 45 of http://www.xilinx.com/support/documentation/user_guides/ug381.pdf, which has a lengthy description of the behaviour of pins before configuration completes. In summary, they have a built-in pull-up, which you should be able to disable by tying a control line down.

The device's pull-up current is specified in the datasheet, and it's believable that 10K might not be enough to overcome it.

The Spartan 6 documentation is ridiculously fragmented into umpteen separate documents - I wouldn't pretend you need to read them all from cover-to-cover, but you do need to be able to find your way around them - they're all linked from that document you linked to. I think if I was starting a Spartan-6 design right now I'd download the whole lot and splice them into one big PDF before I started.

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  • \$\begingroup\$ just made some edits to my question. Assuming that the pins are pulled up during the configuration, pulling down them with 10k does not help. Do they need stronger pulldown? \$\endgroup\$ – Nazar Oct 30 '15 at 21:52
  • \$\begingroup\$ Thank you. It would take me some time to find this info among the documentation sheets. \$\endgroup\$ – Nazar Oct 30 '15 at 22:04
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I have had some first hand experience with the issue of the Xilinx Spartan 6 pins getting pulled up high during configuration at either power up reading from the initialization SPI flash chip or at programming time. Putting pull down resistors to overcome the onboard pullups can be problematic because in the normal operational mode the FPGA output pin has to source extra drive current out its driver to overcome the pulldown and get the signal to a high level.

I found that there are two fairly decent ways to deal with this.

1) Change your FPGA design to emit the control signal off the chip with its idle (non active) state as a high level as opposed to a low level. Then buffer the FPGA pin signal through an inverter chip to get your desired low idle level signal.

2) Another scheme, which is particularly applicable to applications where FPGA outputs are going to circuitry that is powered down during the time span of the FPGA configuration cycle, is to place a "quick switch" type part in the signal path. The switch is a digital mode transmission gate that is does not become enabled ON until the FPGA emits the DONE signal at the end of configuration. During the configuration time the switch is off and the downwind part of the control signal can be easily be pulled down with a fairly high valued resistor. This high valued resistor can represent a very light additional load on the FPGA output pin once the normal mode is reached and the transmission gate is turned on.

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  • 1
    \$\begingroup\$ JOOI, did you try using the HSWAPEN to disable the pull-ups? \$\endgroup\$ – user1844 Oct 31 '15 at 9:31

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