I would like to have a control signal that stays low all the time and goes hi only when I tell it to. Initializing the pin in the entity does not seem to set the value to zero (xc6slx25-3ftg256):
Entity myEntity IS PORT( -- clock and other IOs mySignal : OUT STD_LOGIC := '0' ); END myEntity; ARCHITECTURE structural OF myModule IS BEGIN -- ... -- at some point I set mySignal to 'HI' mySignal <= '1'; -- ... END structural;
-- other nets NET "mySignal" LOC = "H15";
I realize that during the configuration, the FPGA structure is not set, so it may have some random values on its outputs. However, after pulling down the pin with 10k, it still stays 'HI' during reset and configuration. How to make it stay low?